DDR3-P-E3-UT1

DDR3-P-E3-UT1 Datasheet

DDR3 SDRAM Controller

Part	Datasheet
DDR3-P-E3-UT1	DDR3-P-E3-UT1 (pdf)

Related Parts	Information
DDR3-P-E3-U1	DDR3-P-E3-U1

PDF Datasheet Preview
DDR3 SDRAM Controller Home > Products > Intellectual Property > Lattice IP Cores > DDR3 SDRAM Controller DDR3 SDRAM Controller Overview The Lattice Double Data Rate DDR3 Synchronous Dynamic Random Access Memory SDRAM Controller is a general-purpose memory controller that interfaces with industry standard DDR3 memory devices/modules compliant with JESD79-3, DDR3 SDRAM Standard, and provides a generic command interface to user applications. The DDR3 SDRAM is the next-generation DDR SDRAM memory technology which features faster speed, mitigated SSO, and reduced routing due to “fly-by” routing signals to SDRAM instead of low skew tree distribution. This core reduces the effort required to integrate the DDR3 memory controller with the remainder of the application and minimizes the need to directly deal with the DDR3 memory interface. Support for all LatticeECP3 “EA” devices Interfaces to Industry Standard DDR3 SDRAM components and modules compliant with JESD79-3, DDR3 SDRAM Standard Interfaces to DDR3 SDRAM at speeds up to 400 MHz / 800 Mbps in -8 speed grade devices Supports memory data path widths of -8, -16, -24, -32, -40, -48, -56, -64 and -72 bits Supports x4, x8, and x16 device configurations Support for unbuffered DDR3 DIMM and DDR3 RDIMM module Supports up to one DIMM and two ranks per DIMM Programmable burst lengths of 8 fixed , chopped 4 or 8 on-the-fly , or chopped 4 fixed Programmable CAS latency Programmable CAS Write Latency Read burst type of nibble sequential or interleave Supports automatic DDR3 SDRAM initialization and refresh Automatic Write Leveling for each DQS for DIMM applications. Option to switch of write leveling for On-board memory applications. Supports Power Down Mode Supports Dynamic On-Die Termination ODT controls Termination Data Strobe TDQS for x8 widths only LatticeECP3 I/O primitives manage read skews Read Leveling equivalent Automatic Programmable Interval Refresh or User Initiated Refresh Option for controlling memory reset outside the controller The DDR3 SDRAM Controller is available as an IPexpress user configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased. 10/10/2011 DDR3 SDRAM Controller Performance and Resource Utilization Parameters SLICEs LatticeECP31, 2 LUTs Registers fMAX MHz Data Bus Width 8 x8 1741 2526 1772 400 MHz 800 Mbps Data Bus Width 16 x8 1924 2672 2096 400 MHz 800 Mbps Data Bus Width 24 x8 2108 2800 2439 400 MHz 800 Mbps Data Bus Width 32 x8 2303 2913 2789 400 MHz 800 Mbps Data Bus Width 40 x8 2298 2966 2692 Ordering Information Family LatticeECP3 EA DDR3-P-E3-U1 IP Version Evaluate To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide. Purchase To find out how to purchase the IP Core, please contact your local Lattice Sales Office. 10/10/2011

PDF Datasheet Preview

DDR3 SDRAM Controller

Home > Products > Intellectual Property > Lattice IP Cores > DDR3 SDRAM Controller

DDR3 SDRAM Controller

Overview

The Lattice Double Data Rate DDR3 Synchronous Dynamic Random Access Memory SDRAM Controller is a general-purpose memory controller that interfaces with industry standard DDR3 memory devices/modules compliant with JESD79-3, DDR3 SDRAM Standard, and provides a generic command interface to user applications. The DDR3 SDRAM is the next-generation DDR SDRAM memory technology which features faster speed, mitigated SSO, and reduced routing due to “fly-by” routing signals to SDRAM instead of low skew tree distribution. This core reduces the effort required to integrate the DDR3 memory controller with the remainder of the application and minimizes the need to directly deal with the DDR3 memory interface.

Support for all LatticeECP3 “EA” devices Interfaces to Industry Standard DDR3 SDRAM components and modules compliant with JESD79-3, DDR3 SDRAM Standard Interfaces to DDR3 SDRAM at speeds up to 400 MHz / 800 Mbps in -8 speed grade devices Supports memory data path widths of -8, -16, -24, -32, -40, -48, -56, -64 and -72 bits Supports x4, x8, and x16 device configurations Support for unbuffered DDR3 DIMM and DDR3 RDIMM module Supports up to one DIMM and two ranks per DIMM Programmable burst lengths of 8 fixed , chopped 4 or 8 on-the-fly , or chopped 4 fixed Programmable CAS latency

Programmable CAS Write Latency Read burst type of nibble sequential or interleave Supports automatic DDR3 SDRAM initialization and refresh Automatic Write Leveling for each DQS for DIMM applications. Option to switch of write leveling for On-board memory applications. Supports Power Down Mode Supports Dynamic On-Die Termination ODT controls Termination Data Strobe TDQS for x8 widths only LatticeECP3 I/O primitives manage read skews Read Leveling equivalent Automatic Programmable Interval Refresh or User Initiated Refresh Option for controlling memory reset outside the controller

The DDR3 SDRAM Controller is available as an IPexpress user configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.
10/10/2011

DDR3 SDRAM Controller

Performance and Resource Utilization

Parameters

SLICEs

LatticeECP31, 2

LUTs

Registers
fMAX MHz

Data Bus Width 8 x8
1741
2526
1772
400 MHz 800 Mbps

Data Bus Width 16 x8
1924
2672
2096
400 MHz 800 Mbps

Data Bus Width 24 x8
2108
2800
2439
400 MHz 800 Mbps

Data Bus Width 32 x8
2303
2913
2789
400 MHz 800 Mbps

Data Bus Width 40 x8
2298
2966
2692
Ordering Information

Family

LatticeECP3 EA

DDR3-P-E3-U1

IP Version Evaluate To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide. Purchase To find out how to purchase the IP Core, please contact your local Lattice Sales Office.
10/10/2011

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived DDR3-P-E3-UT1 Datasheet file may be downloaded here without warranties.

Datasheet ID: DDR3-P-E3-UT1 645460