DAFIR-GEN-SC-UT2

DAFIR-GEN-SC-UT2 Datasheet

Part Number DAFIR-GEN-E3-U2 DAFIR-GEN-PM-U2 DAFIR-GEN-P2-U2 DAFIR-GEN-E2-U2 DAFIR-GEN-SC-U2 DAFIR-GEN-X2-U2 DAFIR-GEN-XM-U2

Part	Datasheet
DAFIR-GEN-SC-UT2	DAFIR-GEN-SC-UT2 (pdf)

Related Parts	Information
DAFIR-GEN-P2-U1	DAFIR-GEN-P2-U1
DAFIR-GEN-X2-U1	DAFIR-GEN-X2-U1
DAFIR-GEN-X2-UT1	DAFIR-GEN-X2-UT1
DAFIR-GEN-SC-UT1	DAFIR-GEN-SC-UT1
DAFIR-GEN-XM-UT1	DAFIR-GEN-XM-UT1
DAFIR-GEN-SC-U1	DAFIR-GEN-SC-U1
DAFIR-GEN-PM-UT1	DAFIR-GEN-PM-UT1
DAFIR-GEN-XM-U1	DAFIR-GEN-XM-U1
DAFIR-GEN-E2-U1	DAFIR-GEN-E2-U1
DAFIR-GEN-E3-UT1	DAFIR-GEN-E3-UT1
DAFIR-GEN-E2-UT1	DAFIR-GEN-E2-UT1
DAFIR-GEN-PM-U1	DAFIR-GEN-PM-U1
DAFIR-GEN-E3-U1	DAFIR-GEN-E3-U1
DAFIR-GEN-XM-UT2	DAFIR-GEN-XM-UT2
DAFIR-GEN-XM-U2	DAFIR-GEN-XM-U2
DAFIR-GEN-P2-U2	DAFIR-GEN-P2-U2
DAFIR-GEN-X2-U2	DAFIR-GEN-X2-U2
DAFIR-GEN-SC-U2	DAFIR-GEN-SC-U2
DAFIR-GEN-E2-U2	DAFIR-GEN-E2-U2
DAFIR-GEN-PM-UT2	DAFIR-GEN-PM-UT2
DAFIR-GEN-E3-UT2	DAFIR-GEN-E3-UT2
DAFIR-GEN-PM-U2	DAFIR-GEN-PM-U2
DAFIR-GEN-E2-UT2	DAFIR-GEN-E2-UT2
DAFIR-GEN-X2-UT2	DAFIR-GEN-X2-UT2
DAFIR-GEN-P2-UT2	DAFIR-GEN-P2-UT2
DAFIR-GEN-E3-U2	DAFIR-GEN-E3-U2

PDF Datasheet Preview
Distributed Arithmetic FIR DA-FIR Home > Products > Intellectual Property > Lattice IP Cores > Distributed Arithmetic FIR DA-FIR Distributed Arithmetic FIR DA-FIR Filter Generator Overview The Lattice Distributed Arithmetic Finite Impulse Response DA-FIR Filter Generator IP implements a highly configurable, multi-channel DA-FIR filter, using distributed arithmetic algorithms implemented in FPGA Look Up Table LUT or Embedded Block Memory EBR to efficiently support the sum-of-product calculations required to perform the filter function. These techniques generate very area-efficient utilization of the FPGA LUTs while enabling savings of multiply-accumulate blocks sysDSP for other design logic. As a result, the DA-FIR Filter Generator IP core is extremely useful for implementing custom DSP blocks in Lattice FPGAs. Please refer to the user's guide to determine which cores are available for each device family. Variable number of taps up to 1024 Multi-channel support up to 32 channels Polyphase interpolation/decimation filters Halfband filters Interpolation and Decimation ratios from 2 to 32 Input data widths from 4 to 32 bits Coefficient widths from 4 to 32 bits Signed or unsigned data and coefficients Selectable rounding truncation, rounding away from zero, convergent rounding Optional saturation logic for overflow handling Full precision arithmetic Specification of fractional inputs and outputs Support for both serial and parallel filters, with user specified degree of parallelism. Configurable pipelining to increase performance Optimizations based on filter characteristics symmetry and halfband . Handshake signals to facilitate smooth interfacing Performance and Resource Utilization Channels 1 Taps 16 Interpolation Disable LatticeECP31 DWidth Round SLICEs TRUN LUTs 348 EBRs - Registers 476 Fmax 318 Disable TRUN Enable TRUN Performance and utilization data are generated targeting a LFE3-70E-7FN484CES device using Lattice Diamond and Synplify Pro D2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family. Channels 1 Taps 16 Interpolation Disable LatticeECP2M/S1 DWidth Round SLICEs TRUN LUTs 378 EBRs - Registers 481 Fmax 343 Disable TRUN 10/10/2011 Distributed Arithmetic FIR DA-FIR Channels 1 Taps 36 Interpolation Enable DWidth 12 Round TRUN SLICEs 625 Ordering Information Family LatticeECP3 LatticeECP2M LatticeECP2 LatticeECP/EC LatticeSC LatticeXP2 LatticeXP Part Number DAFIR-GEN-E3-U2 DAFIR-GEN-PM-U2 DAFIR-GEN-P2-U2 DAFIR-GEN-E2-U2 DAFIR-GEN-SC-U2 DAFIR-GEN-X2-U2 DAFIR-GEN-XM-U2 IP Version Evaluate To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide. Purchase To find out how to purchase the IP Core, please contact your local Lattice Sales Office. 10/10/2011

PDF Datasheet Preview

Distributed Arithmetic FIR DA-FIR

Home > Products > Intellectual Property > Lattice IP Cores > Distributed Arithmetic FIR DA-FIR

Distributed Arithmetic FIR DA-FIR Filter Generator

Overview

The Lattice Distributed Arithmetic Finite Impulse Response DA-FIR Filter Generator IP implements a highly configurable, multi-channel DA-FIR filter, using distributed arithmetic algorithms implemented in FPGA Look Up Table LUT or Embedded Block Memory EBR to efficiently support the sum-of-product calculations required to perform the filter function. These techniques generate very area-efficient utilization of the FPGA LUTs while enabling savings of multiply-accumulate blocks sysDSP for other design logic. As a result, the DA-FIR Filter Generator IP core is extremely useful for implementing custom DSP blocks in Lattice FPGAs. Please refer to the user's guide to determine which cores are available for each device family.

Variable number of taps up to 1024 Multi-channel support up to 32 channels Polyphase interpolation/decimation filters Halfband filters Interpolation and Decimation ratios from 2 to 32 Input data widths from 4 to 32 bits Coefficient widths from 4 to 32 bits Signed or unsigned data and coefficients Selectable rounding truncation, rounding away from zero, convergent rounding

Optional saturation logic for overflow handling Full precision arithmetic Specification of fractional inputs and outputs Support for both serial and parallel filters, with user specified degree of parallelism. Configurable pipelining to increase performance Optimizations based on filter characteristics symmetry and halfband . Handshake signals to facilitate smooth interfacing

Performance and Resource Utilization

Channels 1

Taps 16

Interpolation Disable

LatticeECP31 DWidth Round SLICEs

TRUN

LUTs 348

EBRs -

Registers 476

Fmax 318

Disable

TRUN

Enable

TRUN

Performance and utilization data are generated targeting a LFE3-70E-7FN484CES device using Lattice Diamond and Synplify Pro D2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.

Channels 1

Taps 16

Interpolation Disable

LatticeECP2M/S1 DWidth Round SLICEs

TRUN

LUTs 378

EBRs -

Registers 481

Fmax 343

Disable

TRUN
10/10/2011

Distributed Arithmetic FIR DA-FIR

Channels 1

Taps 36

Interpolation Enable

DWidth 12

Round TRUN

SLICEs 625
Ordering Information

Family LatticeECP3 LatticeECP2M LatticeECP2 LatticeECP/EC LatticeSC LatticeXP2 LatticeXP

Part Number DAFIR-GEN-E3-U2 DAFIR-GEN-PM-U2 DAFIR-GEN-P2-U2 DAFIR-GEN-E2-U2 DAFIR-GEN-SC-U2 DAFIR-GEN-X2-U2 DAFIR-GEN-XM-U2

IP Version Evaluate To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide. Purchase To find out how to purchase the IP Core, please contact your local Lattice Sales Office.
10/10/2011

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived DAFIR-GEN-SC-UT2 Datasheet file may be downloaded here without warranties.

Datasheet ID: DAFIR-GEN-SC-UT2 645458