M-8888-01SM

M-8888-01SM Datasheet

M-8888

Part	Datasheet
M-8888-01SM	M-8888-01SM (pdf)

Related Parts	Information
M-8888-01P	M-8888-01P
M-8888-01T	M-8888-01T

PDF Datasheet Preview
• Advanced CMOS technology for low power consumption and increased noise immunity • Complete DTMF transmitter/receiver in a single chip Standard 8051, 8086/8 microprocessor port • Central office quality and performance • Adjustable guard time • Automatic tone burst mode • Call progress mode • Single +5 Volt power supply • 20-pin DIP and SOIC packages • 2 MHz microprocessor port operation • Inexpensive MHz crystal Applications Paging systems • Repeater systems/mobile radio • Interconnect dialers • PBX systems • Computer systems • Fax machines • Pay telephone • Credit card verification M-8888 DTMF Transceiver The M-8888 is a complete DTMF Transmitter Receiver that features adjustable guard time, automatic tone burst mode, call progress mode, and a fully compatible 8051, 8086/8 microprocessor interface. The receiver portion is based on the industry standard M-8870 DTMF Receiver, while the transmitter uses a switched-capacitor digital-to-analog converter for lowdistortion, highly accurate DTMF signaling. Tone bursts can be transmitted with precise timing by making use of the automatic tone burst mode. To analyze call progress tones, a call progress filter can be selected by an external microprocessor. Ordering Information Part # M-8888-01P 20-pin plastic DIP M-8888-01SM 20-pin plastic SOIC M-8888-01T 20-pin plastic SOIC,Tape and Reel Pin Connections Block Diagram DS-M8888-R1 M-8888 Single-Ended Input Configuration Differential Input Configuration Functional Description M-8888 functions consist of a high-performance DTMF receiver with an internal gain setting amplifier and a DTMF generator that contains a tone burst counter for generating precise tone bursts and pauses. The call progress mode, when selected, allows the detection of call progress tones. A standard 8051, 8086/8 series microprocessor interface allows access to an internal status register, two control registers, and two data registers. ing the amplifier inputs at VDD/2. Provisions are made for the connection of a feedback resistor to the op-amp output GS for gain adjustment. In a single-ended configuration, the input pins should be connected as shown in the Single-Ended Input Configuration above. Differential Input Configuration above shows the necessary connections for a differential input configuration. Input Configuration The input arrangement consists of a differential input operational amplifier and bias sources VREF for bias- Receiver Section The low and high group tones are separated by applying the DTMF signal to the inputs of two sixth-order Pin Functions Name IN+ INGS VREF VSS OSC1 OSC2 TONE WR CS RS0 RD IRQ /CP D0-D3 ESt St/GT Noninverting op-amp input. Inverting op-amp input. Gain select. Gives access to output of front end differential amplifier for connection of feedback resistor. Reference voltage output. Nominally VDD/2 is used to bias inputs at mid-rail. Negative power supply input. DTMF clock/oscillator input. Clock output. A MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. Dual tone multifrequency DTMF output. Write input. A low on this pin when CS is low enables data transfer from the microprocessor. TTL compatible. Chip select. TTL input CS = 0 to select the chip . Register select input. See Internal Register Functions on page TTL compatible. Read input. A low on this pin when CS is low enables data transfer to the microprocessor. TTL compatible.. Interrupt request to microprocessor open-drain output . Also, when call progress CP mode has been selected and interrupt enabled, the IRQ/CP pin will output a rectangular wave signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Timing Diagrams on page Microprocessor data bus. TTL compatible. Early steering output. Presents a logic high once the digital algorithm has detected a valid tone pair signal condition . Any momentary loss of signal condition will cause ESt to return to a logic low. Steering input/guard time output bidirectional . A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant its state is a function of ESt and the voltage on St. Positive power supply input. M-8888 switched capacitor bandpass filters with bandwidths that correspond to the low and high group frequencies listed in the Tone Encoding/Decoding below. The low group filter incorporates notches at 350 and 440 Hz, providing excellent dial tone rejection. Each filter output is followed by a single-order switched capacitor filter that smoothes the signals prior to limiting. Limiting is performed by high-gain comparators with hysteresis to prevent detection of unwanted low-level signals. The comparator outputs provide full-rail logic swings at the incoming DTMF signal frequencies. A decoder employs digital counting techniques to determine the frequencies of the incoming tones, and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals such as voice , while tolerating small deviations in frequency. The algorithm provides an optimum combination of immunity to talkoff with tolerance to interfering frequencies third tones and noise. When the detector recognizes the presence of two valid tones referred to as signal condition , the early steering ESt output goes to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state. Tone Encoding/Decoding FLOW FHIGH Digit D3 D2 D1 697 1209 1 697 1336 2 697 1477 3 770 1209 4 770 1336 5 770 1477 6

PDF Datasheet Preview

• Advanced CMOS technology for low power consumption and increased noise immunity
• Complete DTMF transmitter/receiver in a single chip Standard 8051, 8086/8 microprocessor port
• Central office quality and performance
• Adjustable guard time
• Automatic tone burst mode
• Call progress mode
• Single +5 Volt power supply
• 20-pin DIP and SOIC packages
• 2 MHz microprocessor port operation
• Inexpensive MHz crystal

Applications Paging systems
• Repeater systems/mobile radio
• Interconnect dialers
• PBX systems
• Computer systems
• Fax machines
• Pay telephone
• Credit card verification

M-8888

DTMF Transceiver

The M-8888 is a complete DTMF Transmitter Receiver that features adjustable guard time, automatic tone burst mode, call progress mode, and a fully compatible 8051, 8086/8 microprocessor interface. The receiver portion is based on the industry standard M-8870 DTMF Receiver, while the transmitter uses a switched-capacitor digital-to-analog converter for lowdistortion, highly accurate DTMF signaling. Tone bursts can be transmitted with precise timing by making use of the automatic tone burst mode. To analyze call progress tones, a call progress filter can be selected by an external microprocessor.
Ordering Information

Part #

M-8888-01P
20-pin plastic DIP

M-8888-01SM 20-pin plastic SOIC

M-8888-01T
20-pin plastic SOIC,Tape and Reel

Pin Connections

Block Diagram

DS-M8888-R1

M-8888

Single-Ended Input Configuration

Differential Input Configuration

Functional Description

M-8888 functions consist of a high-performance DTMF receiver with an internal gain setting amplifier and a DTMF generator that contains a tone burst counter for generating precise tone bursts and pauses. The call progress mode, when selected, allows the detection of call progress tones. A standard 8051, 8086/8 series microprocessor interface allows access to an internal status register, two control registers, and two data registers.
ing the amplifier inputs at VDD/2. Provisions are made for the connection of a feedback resistor to the op-amp output GS for gain adjustment. In a single-ended configuration, the input pins should be connected as shown in the Single-Ended Input Configuration above. Differential Input Configuration above shows the necessary connections for a differential input configuration.

Input Configuration

The input arrangement consists of a differential input operational amplifier and bias sources VREF for bias-

Receiver Section

The low and high group tones are separated by applying the DTMF signal to the inputs of two sixth-order

Pin Functions

Name IN+ INGS VREF VSS OSC1 OSC2 TONE WR CS RS0 RD

IRQ /CP

D0-D3 ESt

St/GT

Noninverting op-amp input. Inverting op-amp input. Gain select. Gives access to output of front end differential amplifier for connection of feedback resistor. Reference voltage output. Nominally VDD/2 is used to bias inputs at mid-rail. Negative power supply input. DTMF clock/oscillator input. Clock output. A MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. Dual tone multifrequency DTMF output. Write input. A low on this pin when CS is low enables data transfer from the microprocessor. TTL compatible. Chip select. TTL input CS = 0 to select the chip . Register select input. See Internal Register Functions on page TTL compatible. Read input. A low on this pin when CS is low enables data transfer to the microprocessor. TTL compatible.. Interrupt request to microprocessor open-drain output . Also, when call progress CP mode has been selected and interrupt enabled, the IRQ/CP pin will output a rectangular wave signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Timing Diagrams on page Microprocessor data bus. TTL compatible.

Early steering output. Presents a logic high once the digital algorithm has detected a valid tone pair signal condition . Any momentary loss of signal condition will cause ESt to return to a logic low.

Steering input/guard time output bidirectional . A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant its state is a function of ESt and the voltage on St.

Positive power supply input.

M-8888
switched capacitor bandpass filters with bandwidths that correspond to the low and high group frequencies listed in the Tone Encoding/Decoding below. The low group filter incorporates notches at 350 and 440 Hz, providing excellent dial tone rejection. Each filter output is followed by a single-order switched capacitor filter that smoothes the signals prior to limiting. Limiting is performed by high-gain comparators with hysteresis to prevent detection of unwanted low-level signals. The comparator outputs provide full-rail logic swings at the incoming DTMF signal frequencies.

A decoder employs digital counting techniques to determine the frequencies of the incoming tones, and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals such as voice , while tolerating small deviations in frequency. The algorithm provides an optimum combination of immunity to talkoff with tolerance to interfering frequencies third tones and noise. When the detector recognizes the presence of two valid tones referred to as signal condition , the early steering ESt output goes to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state.

Tone Encoding/Decoding

FLOW FHIGH Digit D3

D2 D1
697 1209 1
697 1336 2
697 1477 3
770 1209 4
770 1336 5
770 1477 6

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived M-8888-01SM Datasheet file may be downloaded here without warranties.

Datasheet ID: M-8888-01SM 523332