GCIXP1200GA

GCIXP1200GA Datasheet

i GCIXP1200XX FPO# INTEL M C 2001

Part	Datasheet
GCIXP1200GA	GCIXP1200GA (pdf)

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IXP1200 Network Processor Product Features Datasheet The IXP1200 Network Processor delivers high-performance processing power and flexibility to a wide variety of LAN and telecommunications products. Distinguishing features of the IXP1200 are the performance of ASIC hardware along with programmability of a microprocessor. s Applications s Industry Standard 64-bit SDRAM Interface Multi-layer LAN Switches Peak bandwidth of up to 928 Mbytes/sec Multi-protocol Telecommunications Products Address up to 256 Mbytes of SDRAM Broadband Cable Products Memory bandwidth improvement through Remote Access Devices bank switching Intelligent PCI adapters Read-modify-write support s Integrated StrongARM Core Byte aligner/merger High-performance, low-power, 32-bit s Industry Standard 32-bit SRAM Interface Embedded RISC processor Peak bandwidth of up to 464 Mbytes/sec 16 Kbyte instruction cache Address up to 8 Mbytes of SRAM 8 Kbyte data cache Up to 8 Mbytes FlashROM for booting 512 byte mini-cache for data that is used once StrongARM Core and then discarded Supports atomic push/pop operations Write buffer Supports atomic bit set and bit clear Memory management unit operations Access to IXP1200 FBI Unit, PCI Unit and Memory bandwidth imporvement by reduced SDRAM Unit via the ARM* AMBA Bus read/write turnaround bus cycles s Six Integrated Programmable Microengines s Other Integrated Features Operating frequency of up to 232 MHz Hardware Hash Unit for generation of 48- or Multi-thread support of four threads per Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at Copyright Intel Corporation, 2001 Intel is a registered trademark of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others. Datasheet IXP1200 Network Processor Contents Product Description 9 Related Conventions Functional StrongARM Microengines FBI Unit and the IX IX Bus Access Behavior Reset and Idle Bus Considerations SDRAM and SRAM SDRAM Unit SDRAM Bus Access Behavior SDRAM Configurations SRAM Types SRAM Configurations BootROM Configurations SRAM Bus Access Behavior PCI Unit PCI Arbitration and Central Function Support Device Reset Hardware Initiated Software Initiated Reset PCI Initiated Reset Watchdog Timer Initiated Reset Signal Description Pinout Pin Type Legend Pin Description, Grouped by Processor Support SRAM Interface Pins SDRAM Interface Pins IX Bus Interface General Purpose Serial Port UART Pins PCI Interface Pins Power Supply Pins IEEE Interface Pins Miscellaneous Test Pin Usage Summary Pin/Signal Signals Listed in Alphabetical Order Datasheet IXP1200 Network Processor IX Bus Pins Function Listed by Operating 52 IX Bus Decode Table Listed by Operating Mode Type 62 Pin State During 64 Pullup/Pulldown and Unused Pin Guidelines 66 Electrical Specifications 67 Absolute Maximum Ratings 67 DC 70 Type 1 Driver DC Specifications 70 Type 2 Driver DC Specifications 71 Overshoot/Undershoot Specifications 71 AC Specifications 72 Clock Timing Specifications 72 PXTAL Clock 72 PXTAL Clock Oscillator 73 PCI 73 PCI Electrical Specification 73 PCI Clock Signal AC Parameter Measurements....................... 73 PCI Bus Signals 75 76 Reset Timings Specification 76 IEEE 77 IEEE Timing Specifications 78 IX 80 FCLK Signal AC Parameter 80 IX Bus Signals Timing 81 IX Bus 83 117 TK_IN/TK_OUT 120 SRAM Interface 120 SRAM SCLK Signal AC Parameter Measurements 120 SRAM Bus Signal Timing 122 SRAM Bus - SRAM Signal Protocol and Timing 124 SRAM Bus - BootROM and SlowPort Timings........................ 128 SRAM Bus - BootRom Signal Protocol and Timing................. 128 SRAM Bus - Slow-Port Device Signal Protocol and Timing 131 SDRAM Interface 135 SDCLK AC Parameter 135 SDRAM Bus Signal Timing 136 SDRAM Signal Protocol 137 Asynchronous Signal Timing 141 Mechanical 142 Package Dimensions 142 IXP1200 Package Dimensions mm 144 Figures 1 2 3 4 Block 9 IXP1200 System Block Diagram 10 SDRAM Unit Block Diagram 16 SRAM Unit Block Diagram 18 Datasheet IXP1200 Network Processor Reset Logic Pinout 64-Bit Bidirectional IX Bus, 1-2 MAC 64-Bit Bidirectional IX Bus, 1-2 MAC Mode, FastPort Device 64-Bit Bidirectional IX Bus, 3+ MAC 10 32-Bit Unidirectional IX Bus, 1-2 MAC Mode 11 32-bit Unidirectional IX Bus, 3+ MAC Mode 3-4 MACs Supported 12 Typical IXP1200 Heatsink 13 PXTAL Clock Input 14 PCI Clock Signal AC Parameter

PDF Datasheet Preview

IXP1200 Network Processor

Product Features

Datasheet

The IXP1200 Network Processor delivers high-performance processing power and flexibility to a wide variety of LAN and telecommunications products. Distinguishing features of the IXP1200 are the performance of ASIC hardware along with programmability of a microprocessor.
s Applications
s Industry Standard 64-bit SDRAM Interface

Multi-layer LAN Switches

Peak bandwidth of up to 928 Mbytes/sec

Multi-protocol Telecommunications Products Address up to 256 Mbytes of SDRAM

Broadband Cable Products

Memory bandwidth improvement through

Remote Access Devices
bank switching

Intelligent PCI adapters

Read-modify-write support
s Integrated StrongARM Core

Byte aligner/merger

High-performance, low-power, 32-bit
s Industry Standard 32-bit SRAM Interface

Embedded RISC processor

Peak bandwidth of up to 464 Mbytes/sec
16 Kbyte instruction cache

Address up to 8 Mbytes of SRAM
8 Kbyte data cache

Up to 8 Mbytes FlashROM for booting
512 byte mini-cache for data that is used once

StrongARM Core
and then discarded

Supports atomic push/pop operations

Write buffer

Supports atomic bit set and bit clear

Memory management unit
operations

Access to IXP1200 FBI Unit, PCI Unit and

Memory bandwidth imporvement by reduced

SDRAM Unit via the ARM* AMBA Bus
read/write turnaround bus cycles
s Six Integrated Programmable Microengines s Other Integrated Features

Operating frequency of up to 232 MHz

Hardware Hash Unit for generation of 48- or

Multi-thread support of four threads per
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at

Copyright Intel Corporation, 2001 Intel is a registered trademark of Intel Corporation or its subsidiaries in the United States and other countries *Other names and brands may be claimed as the property of others.

Datasheet

IXP1200 Network Processor

Contents

Product Description 9

Related

Conventions

Functional

StrongARM* Microengines FBI Unit and the IX

IX Bus Access Behavior Reset and Idle Bus Considerations

SDRAM and SRAM SDRAM Unit SDRAM Bus Access Behavior SDRAM Configurations SRAM Types SRAM Configurations BootROM Configurations SRAM Bus Access Behavior

PCI Unit PCI Arbitration and Central Function Support

Device Reset Hardware Initiated Software Initiated Reset PCI Initiated Reset Watchdog Timer Initiated Reset

Signal Description

Pinout Pin Type Legend Pin Description, Grouped by

Processor Support SRAM Interface Pins SDRAM Interface Pins IX Bus Interface General Purpose Serial Port UART Pins PCI Interface Pins Power Supply Pins IEEE Interface Pins Miscellaneous Test Pin Usage Summary Pin/Signal Signals Listed in Alphabetical Order

Datasheet

IXP1200 Network Processor

IX Bus Pins Function Listed by Operating 52 IX Bus Decode Table Listed by Operating Mode Type 62 Pin State During 64 Pullup/Pulldown and Unused Pin Guidelines 66

Electrical Specifications 67

Absolute Maximum Ratings 67 DC 70

Type 1 Driver DC Specifications 70 Type 2 Driver DC Specifications 71 Overshoot/Undershoot Specifications 71 AC Specifications 72 Clock Timing Specifications 72 PXTAL Clock 72 PXTAL Clock Oscillator 73 PCI 73

PCI Electrical Specification 73 PCI Clock Signal AC Parameter Measurements....................... 73 PCI Bus Signals 75 76 Reset Timings Specification 76 IEEE 77 IEEE Timing Specifications 78 IX 80 FCLK Signal AC Parameter 80 IX Bus Signals Timing 81 IX Bus 83 117 TK_IN/TK_OUT 120 SRAM Interface 120 SRAM SCLK Signal AC Parameter Measurements 120 SRAM Bus Signal Timing 122 SRAM Bus - SRAM Signal Protocol and Timing 124 SRAM Bus - BootROM and SlowPort Timings........................ 128 SRAM Bus - BootRom Signal Protocol and Timing................. 128 SRAM Bus - Slow-Port Device Signal Protocol and Timing 131 SDRAM Interface 135 SDCLK AC Parameter 135 SDRAM Bus Signal Timing 136 SDRAM Signal Protocol 137 Asynchronous Signal Timing 141

Mechanical 142

Package Dimensions 142 IXP1200 Package Dimensions mm 144

Figures
1 2 3 4

Block 9 IXP1200 System Block Diagram 10 SDRAM Unit Block Diagram 16 SRAM Unit Block Diagram 18

Datasheet

IXP1200 Network Processor

Reset Logic

Pinout
64-Bit Bidirectional IX Bus, 1-2 MAC
64-Bit Bidirectional IX Bus, 1-2 MAC Mode, FastPort Device
64-Bit Bidirectional IX Bus, 3+ MAC
10 32-Bit Unidirectional IX Bus, 1-2 MAC Mode
11 32-bit Unidirectional IX Bus, 3+ MAC Mode 3-4 MACs Supported
12 Typical IXP1200 Heatsink
13 PXTAL Clock Input
14 PCI Clock Signal AC Parameter

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Datasheet ID: GCIXP1200GA 638947