KU80386SXTA33

KU80386SXTA33 Datasheet

Part	Datasheet
KU80386SXTA33	KU80386SXTA33 (pdf)

Related Parts	Information
NG80386SXLP25	NG80386SXLP25
KU80386SXTA25	KU80386SXTA25
NG80386SXLP33	NG80386SXLP33
NG80386SXLP20	NG80386SXLP20

PDF Datasheet Preview
Intel386TM SX MICROPROCESSOR Y Full 32-Bit Internal Architecture 8- 16- 32-Bit Data Types 8 General Purpose 32-Bit Registers Y Runs Intel386TM Software in a Cost Effective 16-Bit Hardware Environment Runs Same Applications and O S ’s as the Intel386TM DX Processor Object Code Compatible with 8086 80186 80286 and Intel386TM Processors Y High Performance 16-Bit Data Bus 16 20 25 and 33 MHz Clock Two-Clock Bus Cycles Address Pipelining Allows Use of Slower Cheaper Memories Y Integrated Memory Management Unit Virtual Memory Support Optional On-Chip Paging 4 Levels of Hardware Enforced Protection MMU Fully Compatible with Those of the 80286 and Intel386 DX CPUs Y Virtual 8086 Mode Allows Execution of 8086 Software in a Protected and Paged System Y Large Uniform Address Space 16 Megabyte Physical 64 Terabyte Virtual 4 Gigabyte Maximum Segment Size Y Numerics Support with the Intel387TM SX Math CoProcessor Y On-Chip Debugging Support Including Breakpoint Registers Y Complete System Development Support Software C PL M Assembler Debuggers PMON-386 DX ICETM-386 SX Y High Speed CHMOS IV Technology Y Operating Frequency Standard Intel386 SX -33 -25 -20 -16 Min Max Frequency 4 33 4 25 4 20 4 16 MHz Low Power Intel386 SX -33 -25 -20 -16 -12 Min Max Frequency 2 33 2 25 2 20 2 16 2 12 MHz Y 100-Pin Plastic Quad Flatpack Package See Packaging Outlines and Dimensions 231369 The Intel386TM SX Microprocessor is an entry-level 32-bit CPU with a 16-bit external data bus and a 24-bit external address bus The Intel386 SX CPU brings the vast software library of the Intel386TM Architecture to entry-level systems It provides the performance benefits of a 32-bit programming architecture with the cost savings associated with 16-bit hardware systems Intel386TM SX Pipelined 32-Bit Microarchitecture 240187 47 Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1995 January 1994 Order Number 240187-008 Intel386TM SX MICROPROCESSOR Intel386TM SX MicroProcessor CONTENTS 1 0 PIN DESCRIPTION 2 0 BASE ARCHITECTURE 2 1 Register Set 2 Instruction Set 2 3 Memory Organization 2 4 Addressing Modes 2 5 Data Types 2 6 I O Space 2 7 Interrupts and Exceptions 2 8 Reset and Initialization 2 9 Testability 2 10 Debugging Support 3 0 REAL MODE ARCHITECTURE 3 1 Memory Addressing 3 2 Reserved Locations 3 Interrupts 3 4 Shutdown and Halt 3 5 LOCK Operations 4 0 PROTECTED MODE ARCHITECTURE 4 1 Addressing Mechanism 4 2 Segmentation 4 3 Protection 4 Paging 4 5 Virtual 8086 Environment 6 10 11 12 15 17 20 21 22 23 24 29 33 36 CONTENTS 5 0 FUNCTIONAL DATA 5 1 Signal Description Overview 5 2 Bus Transfer Mechanism 5 3 Memory and I O Spaces 5 4 Bus Functional Description 5 Self-test Signature Identifiers 5 7 Coprocessor Interfacing

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Intel386TM SX MICROPROCESSOR

Y Full 32-Bit Internal Architecture 8- 16- 32-Bit Data Types 8 General Purpose 32-Bit Registers

Y Runs Intel386TM Software in a Cost Effective 16-Bit Hardware Environment Runs Same Applications and O S ’s as the Intel386TM DX Processor Object Code Compatible with 8086 80186 80286 and Intel386TM Processors

Y High Performance 16-Bit Data Bus 16 20 25 and 33 MHz Clock Two-Clock Bus Cycles Address Pipelining Allows Use of Slower Cheaper Memories

Y Integrated Memory Management Unit Virtual Memory Support Optional On-Chip Paging 4 Levels of Hardware Enforced Protection MMU Fully Compatible with Those of the 80286 and Intel386 DX CPUs

Y Virtual 8086 Mode Allows Execution of 8086 Software in a Protected and Paged System

Y Large Uniform Address Space 16 Megabyte Physical 64 Terabyte Virtual 4 Gigabyte Maximum Segment Size

Y Numerics Support with the Intel387TM SX Math CoProcessor

Y On-Chip Debugging Support Including Breakpoint Registers

Y Complete System Development Support Software C PL M Assembler Debuggers PMON-386 DX ICETM-386 SX

Y High Speed CHMOS IV Technology

Y Operating Frequency Standard Intel386 SX -33 -25 -20 -16 Min Max Frequency 4 33 4 25 4 20 4 16 MHz Low Power Intel386 SX -33 -25 -20 -16 -12 Min Max Frequency 2 33 2 25 2 20 2 16 2 12 MHz

Y 100-Pin Plastic Quad Flatpack Package

See Packaging Outlines and Dimensions 231369

The Intel386TM SX Microprocessor is an entry-level 32-bit CPU with a 16-bit external data bus and a 24-bit external address bus The Intel386 SX CPU brings the vast software library of the Intel386TM Architecture to entry-level systems It provides the performance benefits of a 32-bit programming architecture with the cost savings associated with 16-bit hardware systems

Intel386TM SX Pipelined 32-Bit Microarchitecture
240187 47

Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata

COPYRIGHT INTEL CORPORATION 1995

January 1994

Order Number 240187-008

Intel386TM SX MICROPROCESSOR

Intel386TM SX MicroProcessor

CONTENTS
1 0 PIN DESCRIPTION
2 0 BASE ARCHITECTURE 2 1 Register Set 2 Instruction Set 2 3 Memory Organization 2 4 Addressing Modes 2 5 Data Types 2 6 I O Space 2 7 Interrupts and Exceptions 2 8 Reset and Initialization 2 9 Testability 2 10 Debugging Support
3 0 REAL MODE ARCHITECTURE 3 1 Memory Addressing 3 2 Reserved Locations 3 Interrupts 3 4 Shutdown and Halt 3 5 LOCK Operations
4 0 PROTECTED MODE ARCHITECTURE
4 1 Addressing Mechanism 4 2 Segmentation 4 3 Protection 4 Paging 4 5 Virtual 8086 Environment
6 10 11 12 15 17 20 21
22 23
24 29 33 36

CONTENTS
5 0 FUNCTIONAL DATA
5 1 Signal Description Overview
5 2 Bus Transfer Mechanism
5 3 Memory and I O Spaces
5 4 Bus Functional Description
5 Self-test Signature

Identifiers
5 7 Coprocessor Interfacing

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Datasheet ID: KU80386SXTA33 638944