MT16LSDF6464HY-13ED2

MT16LSDF6464HY-13ED2 Datasheet

MT16LSDF3264 L H 256MB MT16LSDF6464 L H 512MB

Part	Datasheet
MT16LSDF6464HY-13ED2	MT16LSDF6464HY-13ED2 (pdf)

Related Parts	Information
MT16LSDF6464HY-133G1	MT16LSDF6464HY-133G1
MT16LSDF6464HY-13EG1	MT16LSDF6464HY-13EG1
MT16LSDF3264HY-13EG4	MT16LSDF3264HY-13EG4
MT16LSDF3264HG-133G4	MT16LSDF3264HG-133G4
MT16LSDF6464HG-133D2	MT16LSDF6464HG-133D2
MT16LSDF6464HY-133D2	MT16LSDF6464HY-133D2

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256MB, 512MB x64, DR 144-PIN SDRAM SODIMM SMALL-OUTLINE SDRAM MODULE MT16LSDF3264 L H 256MB MT16LSDF6464 L H 512MB For the latest data sheet, please refer to the Web site: • PC100- and PC133-compliant, 144-pin, smalloutline, dual in-line memory module SODIMM • Utilizes 100 MHz and 133 MHz SDRAM components • Unbuffered • 256MB 32 Meg x 64 and 512MB 64 Meg x 64 • Single +3.3V power supply • Fully synchronous all signals registered on positive edge of system clock • Internal pipelined operation column address can be changed every clock cycle • Internal SDRAM banks for hiding row access/ precharge • Programmable burst lengths 1, 2, 4, 8, or full page • Auto precharge and auto refresh modes • Self refresh mode standard and low-power • 256MB module 64ms, 4,096-cycle refresh 15.625µs refresh interval 512MB 64ms, 8,192-cycle refresh 7.81µs refresh interval • LVTTL-compatible inputs and outputs • Serial presence-detect SPD • Gold edge connectors Table 1 Timing Parameters CL = CAS READ latency ACCESS TIME MODULE CLOCK SETUP HOLD MARKING FREQUENCY CL = 2 CL = 3 TIME -13E -133 -10E 133 MHz 133 MHz 100 MHz 5.4ns 5.4ns 1.5ns 1.5ns 2ns 0.8ns 0.8ns 1ns Figure 1 144-Pin SODIMM MO-190 PCB height 1.25in 31.75mm Options • Self refresh current Standard Low power • Package 144-pin SODIMM standard 144-pin SODIMM lead-free • Memory Clock/CL 7.5ns 133 MHz /CL = 2 7.5ns 133 MHz /CL = 3 10ns 100 MHz /CL = 2 • PCB Height 1.25in 31.75mm Marking None L1 -13E -133 -10E See page 2 note NOTE Contact Micron for product availability. Table 2 Address Table Refresh count Device banks Device configuration Row addressing Column addressing Module ranks 256MB 4K 4 BA0, BA1 128Mb 16 Meg x 8 4K 1K 2 S0#, S1# 512MB 8K 4 BA0, BA1 256Mb 32 Meg x 8 8K 1K 2 S0#, S1# 2006 Micron Technology, Inc. All rights reserved. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table CAS Latency CL CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQ will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQ will start driving after T1 and the data will be valid by T2, as shown in Figure 4 on page Table 8 on page 10 indicates the operating frequencies at which each CL setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0M2 applies to both READ and WRITE bursts when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location nonburst accesses. 256MB, 512MB x64, DR 144-PIN SDRAM SODIMM Table 8: SPEED -13E -133 -10E CL Table ALLOWABLE OPERATING CLOCK FREQUENCY MHz CL = 2 133 100 CL = 3 < 143 < 133 NA Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved. Commands The Truth Table provides a quick reference of available commands. This is followed by written description of each command. For a more detailed 256MB, 512MB x64, DR 144-PIN SDRAM SODIMM description of commands and operations, refer to the 128Mb or 256Mb SDRAM component data sheet. Table 9 Truth Table SDRAM Commands and DQMB Operation CKE is HIGH for all commands shown except SELF REFRESH NAME FUNCTION CS# RAS# CAS# WE# DQMB ADDR DQ COMMAND INHIBIT NOP NO OPERATION NOP ACTIVE select bank and activate row X Bank/Row X READ select bank and column, and start READ burst L H H L/H8 Bank/Col X WRITE select bank and column, and start WRITE burst L H L/H8 Bank/Col Valid BURST TERMINATE Active PRECHARGE deactivate row in bank or banks Code

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256MB, 512MB x64, DR 144-PIN SDRAM SODIMM

SMALL-OUTLINE SDRAM MODULE

MT16LSDF3264 L H 256MB MT16LSDF6464 L H 512MB

For the latest data sheet, please refer to the Web site:
• PC100- and PC133-compliant, 144-pin, smalloutline, dual in-line memory module SODIMM
• Utilizes 100 MHz and 133 MHz SDRAM components
• Unbuffered
• 256MB 32 Meg x 64 and 512MB 64 Meg x 64
• Single +3.3V power supply
• Fully synchronous all signals registered on positive
edge of system clock
• Internal pipelined operation column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths 1, 2, 4, 8, or full page
• Auto precharge and auto refresh modes
• Self refresh mode standard and low-power
• 256MB module 64ms, 4,096-cycle refresh 15.625µs
refresh interval 512MB 64ms, 8,192-cycle refresh 7.81µs refresh interval
• LVTTL-compatible inputs and outputs
• Serial presence-detect SPD
• Gold edge connectors

Table 1 Timing Parameters

CL = CAS READ latency

ACCESS TIME

MODULE CLOCK

SETUP HOLD

MARKING FREQUENCY CL = 2 CL = 3 TIME
-13E -133 -10E
133 MHz 133 MHz 100 MHz
5.4ns
5.4ns
1.5ns 1.5ns 2ns
0.8ns 0.8ns 1ns

Figure 1 144-Pin SODIMM MO-190

PCB height 1.25in 31.75mm

Options
• Self refresh current Standard Low power
• Package 144-pin SODIMM standard 144-pin SODIMM lead-free
• Memory Clock/CL 7.5ns 133 MHz /CL = 2 7.5ns 133 MHz /CL = 3 10ns 100 MHz /CL = 2
• PCB Height 1.25in 31.75mm

Marking

None L1
-13E -133 -10E

See page 2 note

NOTE Contact Micron for product availability.

Table 2 Address Table

Refresh count Device banks Device configuration Row addressing Column addressing Module ranks
256MB
4K 4 BA0, BA1 128Mb 16 Meg x 8 4K 1K 2 S0#, S1#
512MB
8K 4 BA0, BA1 256Mb 32 Meg x 8 8K 1K 2 S0#, S1#
2006 Micron Technology, Inc. All rights reserved.
The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table

CAS Latency CL

CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQ will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQ will start driving after T1 and the data will be valid by T2, as shown in Figure 4 on page Table 8 on page 10 indicates the operating frequencies at which each CL setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts.

Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0M2 applies to both READ and WRITE bursts when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location nonburst accesses.
256MB, 512MB x64, DR 144-PIN SDRAM SODIMM

Table 8:

SPEED -13E -133 -10E

CL Table

ALLOWABLE OPERATING CLOCK FREQUENCY MHz

CL = 2
133 100

CL = 3
< 143 < 133 NA

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2006 Micron Technology, Inc. All rights reserved.

Commands

The Truth Table provides a quick reference of available commands. This is followed by written description of each command. For a more detailed
256MB, 512MB x64, DR 144-PIN SDRAM SODIMM
description of commands and operations, refer to the 128Mb or 256Mb SDRAM component data sheet.

Table 9 Truth Table SDRAM Commands and DQMB Operation

CKE is HIGH for all commands shown except SELF REFRESH

NAME FUNCTION

CS# RAS# CAS# WE# DQMB ADDR DQ

COMMAND INHIBIT NOP

NO OPERATION NOP

ACTIVE select bank and activate row

X Bank/Row X

READ select bank and column, and start READ burst L H

H L/H8 Bank/Col X

WRITE select bank and column, and start WRITE burst L H

L/H8 Bank/Col Valid

BURST TERMINATE

Active

PRECHARGE deactivate row in bank or banks

Code

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Datasheet ID: MT16LSDF6464HY-13ED2 648316