S82562EH

S82562EH Datasheet

Part	Datasheet
S82562EH	S82562EH (pdf)

Related Parts	Information
GD82550GMSL4ML	GD82550GMSL4ML
GD82550GYSL4Y5	GD82550GYSL4Y5
GD82550ELSL4MK	GD82550ELSL4MK
GD82550EYSL4MJ	GD82550EYSL4MJ

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Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual January 2003 Information in this document is provided in connection with products. This specification, the Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual, is provided “as is” with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82557, 82558, 82559, 82550, and 82551 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. The information in this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Intel Corporation. It is intended to enable the maintenance of the open source PRO/100 drivers for the PRO/100 family of adapters. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at Copyright 2003, Intel Corporation. * Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owners’ benefit, without intent to infringe. Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Contents Contents Document Conventions Device References 2 Numbering 2 Signal Name Representation 2 Memory Alignment Terminology 2 2 Adapter and Controller Overview 5 Adapter Block Diagram 5 Intel Fast Ethernet MAC Features 6 82557 6 82558 6 82559, 82550, 82551, and 82562 Working with the Physical Layer 7 3 Power Management Interface 9 Low Power Mode 9 Device Power States 9 Power Management Registers 9 Link Operation 4 PCI 11 PCI Command Usage 21 Memory Write and Invalidate 22 Read Align 23 Odd Byte Alignment Support 23 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Contents 5 EEPROM Interface 25 6 Host Software Interface 27 The Shared Memory 27 Initializing the LAN Controller 29 LAN Controller Addressing 29 Controlling the 31 Control / Status Registers 31 System Control Block 33 PORT 42 EEPROM Control Register 45 Management Data Interface Control Register 49 Receive Byte Count 51 Early Receive Interrupt 52 Flow Control Register 53 Power Management Driver 54 General Control Register 55 General Status Register 56 Shared Memory 57 Action Commands and Operating 57 Specific Action 59 Receive Operation 97 Command Unit and Receive Unit 103 Starting and Completing Control Commands 103 Generating and acknowledging interrupts 103 Command Unit Control 104 Receive Unit 106 Updating SCB 108 Flow 108 PHY Based Flow Control 109 Frame Based Flow Control 109 Priority Aware Frame Based Flow 113 Half Duplex Flow Control 114 Collision Backoff Modification in Switched 114 7 Physical Layer Interface 115 Management Data Interface MDI 115 MDI Register Set 116 Control Register 0 117 Status Register 118 Identification Registers 2 and 3 118 Auto-Negotiation Advertisement Register 4 119 Auto-Negotiation Link Partner Ability Register 5 120 Auto-Negotiation Expansion Register 6 120 Intel 82555 Specific Registers 122 Status and Control Register 16 122 Special Control Register 123 Clock Synthesis Test and Control Register 124 100BASE-TX Receive False Carrier Counter Register 19 124 100Base-TX Receive Disconnect Counter Register 124 Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Contents 100BASE-TX Receive Error Frame Counter Register 21 125 Receive Symbol Error Counter Register 125 100BASE-TX Receive EOF Error Counter Register 23 10BASE-T Receive EOF Error Counter Register 24 125 10BASE-T Transmit Jabber Detect Counter Register 25 125 Equalizer Control and Status Register 26 126 Special Control Register 127 Auto-Negotiation Functionality Description 128 Parallel 129 Vendor-Specific PHY Programming 130 Intel 82555 TX PHY 130 82558 and 82559 Embedded PHY 130 8 Programming Recommendations 133 Adapter Initialization 133 8255x Initialization PHY Detection and Initialization 133 NOS Specific 134 Transmit Processing 134 Frame Reception 134 Interrupt 135 Appendices A Wake-up Functionality 137 B 82550 and 82551 Specific 153 Figures 1 82557 Network Interface Card Block Diagram 5 2 Command 12 3 Command 13 4 Cache Line 14 5 Base Address Register for Memory Mapping 15 6 Base Address Register for I/O Mapping 7 Expansion ROM Base Address 17 8 8255x Memory Architecture 9 SCB Status 34 10 SCB Command Word 36 11 Self-Test Results Format 43 12 EEPROM Control Register 45 13 EEPROM Read Timing Diagram 48 14 General Action Command Format 58 15 NOP Command Format 59 16 Individual Address Setup Command Format 17 Configure Command Format 61 18 Multicast Setup Command Format 80 19 Transmit Command Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Contents 20 Transmit Buffer 83 21 Load Microcode Command Format 88 22 Dump Command Format 89 23 Diagnose Command Format 95 24 Simplified Memory Structure 98 25 Receive Frame Descriptor Format 98 26 Management Frame 116 27 Command Block 144 Tables Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual Contents

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Intel 8255x 10/100 Mbps Ethernet Controller Family

Open Source Software Developer Manual

January 2003

Information in this document is provided in connection with products. This specification, the Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual, is provided “as is” with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82557, 82558, 82559, 82550, and 82551 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

The information in this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Intel Corporation. It is intended to enable the maintenance of the open source PRO/100 drivers for the PRO/100 family of adapters. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at

Copyright 2003, Intel Corporation.
* Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owners’ benefit, without intent to infringe.

Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual

Contents

Contents

Document Conventions

Device References 2 Numbering 2 Signal Name Representation 2 Memory Alignment Terminology 2
2 Adapter and Controller Overview 5

Adapter Block Diagram 5 Intel Fast Ethernet MAC Features 6
82557 6 82558 6 82559, 82550, 82551, and 82562 Working with the Physical Layer 7
3 Power Management Interface 9

Low Power Mode 9 Device Power States 9 Power Management Registers 9 Link Operation
4 PCI 11

PCI Command Usage 21 Memory Write and Invalidate 22 Read Align 23 Odd Byte Alignment Support 23

Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual

Contents
5 EEPROM Interface 25
6 Host Software Interface 27

The Shared Memory 27 Initializing the LAN Controller 29

LAN Controller Addressing 29 Controlling the 31

Control / Status Registers 31 System Control Block 33 PORT 42 EEPROM Control Register 45 Management Data Interface Control Register 49 Receive Byte Count 51 Early Receive Interrupt 52 Flow Control Register 53 Power Management Driver 54 General Control Register 55 General Status Register 56 Shared Memory 57 Action Commands and Operating 57 Specific Action 59 Receive Operation 97 Command Unit and Receive Unit 103 Starting and Completing Control Commands 103 Generating and acknowledging interrupts 103 Command Unit Control 104 Receive Unit 106 Updating SCB 108 Flow 108 PHY Based Flow Control 109 Frame Based Flow Control 109 Priority Aware Frame Based Flow 113 Half Duplex Flow Control 114 Collision Backoff Modification in Switched 114
7 Physical Layer Interface 115

Management Data Interface MDI 115 MDI Register Set 116

Control Register 0 117 Status Register 118 Identification Registers 2 and 3 118 Auto-Negotiation Advertisement Register 4 119 Auto-Negotiation Link Partner Ability Register 5 120 Auto-Negotiation Expansion Register 6 120 Intel 82555 Specific Registers 122 Status and Control Register 16 122 Special Control Register 123 Clock Synthesis Test and Control Register 124 100BASE-TX Receive False Carrier Counter Register 19 124 100Base-TX Receive Disconnect Counter Register 124

Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual

Contents
100BASE-TX Receive Error Frame Counter Register 21 125 Receive Symbol Error Counter Register 125 100BASE-TX Receive EOF Error Counter Register 23 10BASE-T Receive EOF Error Counter Register 24 125 10BASE-T Transmit Jabber Detect Counter Register 25 125 Equalizer Control and Status Register 26 126 Special Control Register 127 Auto-Negotiation Functionality Description 128 Parallel 129 Vendor-Specific PHY Programming 130 Intel 82555 TX PHY 130 82558 and 82559 Embedded PHY 130
8 Programming Recommendations 133

Adapter Initialization 133 8255x Initialization PHY Detection and Initialization 133 NOS Specific 134

Transmit Processing 134 Frame Reception 134 Interrupt 135

Appendices

A Wake-up Functionality 137 B 82550 and 82551 Specific 153

Figures
1 82557 Network Interface Card Block Diagram 5 2 Command 12 3 Command 13 4 Cache Line 14 5 Base Address Register for Memory Mapping 15 6 Base Address Register for I/O Mapping 7 Expansion ROM Base Address 17 8 8255x Memory Architecture 9 SCB Status 34 10 SCB Command Word 36 11 Self-Test Results Format 43 12 EEPROM Control Register 45 13 EEPROM Read Timing Diagram 48 14 General Action Command Format 58 15 NOP Command Format 59 16 Individual Address Setup Command Format 17 Configure Command Format 61 18 Multicast Setup Command Format 80 19 Transmit Command

Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual

Contents
20 Transmit Buffer 83 21 Load Microcode Command Format 88 22 Dump Command Format 89 23 Diagnose Command Format 95 24 Simplified Memory Structure 98 25 Receive Frame Descriptor Format 98 26 Management Frame 116 27 Command Block 144

Tables

Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual

Contents

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived S82562EH Datasheet file may be downloaded here without warranties.

Datasheet ID: S82562EH 638932