SB80C188EC13

SB80C188EC13 Datasheet

This data sheet replaces the following data sheets 272072-003 80C186EC 272076-003 80C188EC 272332-001 80L186EC 272333-001 80L188EC 272373-001 SB80C188EC SB80L188EC 272372-001 SB80C186EC SB80L186EC

Part	Datasheet
SB80C188EC13	SB80C188EC13 (pdf)

Related Parts	Information
A80C186ECI	A80C186ECI
KU80L186EC13	KU80L186EC13
SB80L188EC13	SB80L188EC13
SB80L188EC16	SB80L188EC16
SB80L186EC13	SB80L186EC13

PDF Datasheet Preview
80C186EC 80C188EC AND 80L186EC 80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS X Fully Static Operation X True CMOS Inputs and Outputs Y Integrated Feature Set Low-Power Static Enhanced 8086 CPU Core Two Independent DMA Supported UARTs each with an Integral Baud Rate Generator Four Independent DMA Channels 22 Multiplexed I O Port Pins Two 8259A Compatible Programmable Interrupt Controllers Three Programmable 16-Bit Timer Counters 32-Bit Watchdog Timer Ten Programmable Chip Selects with Integral Wait-State Generator Memory Refresh Control Unit Power Management Unit On-Chip Oscillator System Level Testing Support ONCE Mode Y Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I O Y Low-Power Operating Modes Idle Mode Freezes CPU Clocks but Keeps Peripherals Active Powerdown Mode Freezes All Internal Clocks Powersave Mode Divides All Clocks by Programmable Prescalar Y Available in Extended Temperature Range b40 C to a85 C Y Supports 80C187 Numerics Processor Extension 80C186EC only Y Package Types 100-Pin EIAJ Quad Flat Pack QFP 100-Pin Plastic Quad Flat Pack PQFP 100-Pin Shrink Quad Flat Pack SQFP Y Speed Versions Available 5V 25 MHz 80C186EC25 80C188EC25 20 MHz 80C186EC20 80C188EC20 13 MHz 80C186EC13 80C188EC13 Y Speed Version Available 3V 16 MHz 80L186EC16 80L188EC16 13 MHz 80L186EC13 80L188EC13 The 80C186EC is a member of the 186 Integrated Processor Family The 186 Integrated Processor Family incorporates several different VLSI devices all of which share a common CPU architecture the 8086 8088 The 80C186EC uses the latest high density CHMOS technology to integrate several of the most common system peripherals with an enhanced 8086 CPU core to create a powerful system on a single monolithic silicon die Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION, 2004 August, 2004 Order Number 272434-006 80C186EC 80C188EC and 80L186EC 80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR CONTENTS INTRODUCTION 80C186EC CORE ARCHITECTURE Bus Interface Unit Clock Generator 80C186EC PERIPHERAL ARCHITECTURE Programmable Interrupt Controllers Timer Counter Unit Serial Communications Unit DMA Unit Chip-Select Unit I O Port Unit Refresh Control Unit Watchdog Timer Unit Power Management Unit 80C187 Interface 80C186EC only ONCE Test Mode PACKAGE INFORMATION Prefix Identification Pin Descriptions Pinout Package Thermal Specifications ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings 8 15 24 CONTENTS Recommended Connections PAGE 25 DC SPECIFICATIONS ICC versus Frequency and Voltage PDTMR Pin Delay Calculation AC SPECIFICATIONS AC Characteristics 80C186EC25 AC Characteristics 80C186EC20 13 AC Characteristics 80L186EC13 AC Characteristics 80L186EC16 Relative Timings Serial Port Mode 0 Timings AC TEST CONDITIONS

PDF Datasheet Preview

80C186EC 80C188EC AND 80L186EC 80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

X Fully Static Operation X True CMOS Inputs and Outputs

Y Integrated Feature Set Low-Power Static Enhanced 8086 CPU Core Two Independent DMA Supported UARTs each with an Integral Baud Rate Generator Four Independent DMA Channels 22 Multiplexed I O Port Pins Two 8259A Compatible Programmable Interrupt Controllers Three Programmable 16-Bit Timer Counters 32-Bit Watchdog Timer Ten Programmable Chip Selects with Integral Wait-State Generator Memory Refresh Control Unit Power Management Unit On-Chip Oscillator System Level Testing Support ONCE Mode

Y Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I O

Y Low-Power Operating Modes Idle Mode Freezes CPU Clocks but Keeps Peripherals Active Powerdown Mode Freezes All Internal Clocks Powersave Mode Divides All Clocks by Programmable Prescalar

Y Available in Extended Temperature Range b40 C to a85 C

Y Supports 80C187 Numerics Processor Extension 80C186EC only

Y Package Types 100-Pin EIAJ Quad Flat Pack QFP 100-Pin Plastic Quad Flat Pack PQFP 100-Pin Shrink Quad Flat Pack SQFP

Y Speed Versions Available 5V 25 MHz 80C186EC25 80C188EC25 20 MHz 80C186EC20 80C188EC20 13 MHz 80C186EC13 80C188EC13

Y Speed Version Available 3V 16 MHz 80L186EC16 80L188EC16 13 MHz 80L186EC13 80L188EC13

The 80C186EC is a member of the 186 Integrated Processor Family The 186 Integrated Processor Family incorporates several different VLSI devices all of which share a common CPU architecture the 8086 8088 The 80C186EC uses the latest high density CHMOS technology to integrate several of the most common system peripherals with an enhanced 8086 CPU core to create a powerful system on a single monolithic silicon die

Other brands and names are the property of their respective owners

Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata

COPYRIGHT INTEL CORPORATION, 2004

August, 2004

Order Number 272434-006
80C186EC 80C188EC and 80L186EC 80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR

CONTENTS

INTRODUCTION
80C186EC CORE ARCHITECTURE Bus Interface Unit Clock Generator
80C186EC PERIPHERAL ARCHITECTURE

Programmable Interrupt Controllers Timer Counter Unit Serial Communications Unit DMA Unit Chip-Select Unit I O Port Unit Refresh Control Unit Watchdog Timer Unit Power Management Unit 80C187 Interface 80C186EC only ONCE Test Mode

PACKAGE INFORMATION Prefix Identification Pin Descriptions Pinout Package Thermal Specifications

ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings
8 15 24

CONTENTS

Recommended Connections

PAGE 25

DC SPECIFICATIONS

ICC versus Frequency and Voltage

PDTMR Pin Delay Calculation

AC SPECIFICATIONS

AC Characteristics 80C186EC25

AC Characteristics 80C186EC20 13

AC Characteristics 80L186EC13

AC Characteristics 80L186EC16

Relative Timings

Serial Port Mode 0 Timings

AC TEST CONDITIONS

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Datasheet ID: SB80C188EC13 638930