IS61LV632A-6TQI

IS61LV632A-6TQI Datasheet

IS61LV632A

Part	Datasheet
IS61LV632A-6TQI	IS61LV632A-6TQI (pdf)

Related Parts	Information
IS61LV632A-6TQI-TR	IS61LV632A-6TQI-TR

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IS61LV632A 32K x 32 SYNCHRONOUS FAST STATIC RAM APRIL 2001 FEATURES • Fast access time: 4 ns-125 MHz 5 ns-100 MHz 6 ns-83 MHz 7 ns-75 MHz 8 ns-66 MHz • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • Power-down control by ZZ input • JEDEC 100-Pin TQFP and PQFP package • 3.3V Vcc and 2.5V VCCQ for 2.5V I/Os • Two Clock enables and one Clock disable to eliminate multiple bank bus contention. • Control pins mode upon power-up MODE in interleave burst mode ZZ in normal operation mode These control pins can be connected to GNDQ or VCCQ to alter their power-up state DESCRIPTION The ISSI IS61LV632A is a high-speed, low-power synchro- nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium , 680X0 , and PowerPC microprocessors. It is organized as 32,768 words by 32 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3 controls DQ17-DQ24, BW4 controls DQ25-DQ32, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP Address Status Processor or ADSC Address Status Cache Controller input pins. Subsequent burst addresses can be generated internally by the IS61LV632A and controlled by the ADV burst address advance input pin. Asynchronous signals include output enable OE , sleep mode input ZZ , clock CLK and burst mode input MODE . A HIGH input on the ZZ pin puts the SRAM in the power-down state. When ZZ is pulled LOW or no connect , the SRAM normally operates after three cycles of the wake-up period. A LOW input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ or no connect on MODE pin selects INTERLEAVED Burst. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. Copyright 2001, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. 1-800-379-4774 04/17/01 IS61LV632A BLOCK DIAGRAM CLK ADV ADSC ADSP 15 A14-A0 GW BWE BW4 CE1 CE2 CE3 ISSI MODE Q0 A0 BINARY COUNTER Q1 A1 ADDRESS REGISTER 32K x 32 MEMORY ARRAY ORDERING INFORMATION Commercial Range 0°C to +70°C Speed ns Order Part Number IS61LV632A-4TQ IS61LV632A-4PQ IS61LV632A-5TQ IS61LV632A-5PQ IS61LV632A-6TQ IS61LV632A-6PQ IS61LV632A-7TQ IS61LV632A-7PQ IS61LV632A-8TQ IS61LV632A-8PQ Package TQFP PQFP TQFP PQFP TQFP PQFP TQFP PQFP TQFP PQFP Industrial Range to +85°C Speed ns Order Part Number IS61LV632A-6TQI IS61LV632A-6PQI IS61LV632A-7TQI IS61LV632A-7PQI IS61LV632A-8TQI IS61LV632A-8PQI Package TQFP PQFP TQFP PQFP TQFP PQFP ISSI ISSI Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel 1-800-379-4774 Fax 408 588-0806 E-mail: Integrated Silicon Solution, Inc. 1-800-379-4774 04/17/01

PDF Datasheet Preview

IS61LV632A
32K x 32 SYNCHRONOUS FAST STATIC RAM

APRIL 2001

FEATURES
• Fast access time:
4 ns-125 MHz 5 ns-100 MHz 6 ns-83 MHz 7 ns-75 MHz 8 ns-66 MHz
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and control
• Pentium or linear burst sequence control using MODE input
• Three chip enables for simple depth expansion and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin TQFP and PQFP package
• 3.3V Vcc and 2.5V VCCQ for 2.5V I/Os
• Two Clock enables and one Clock disable to eliminate multiple bank bus contention.
• Control pins mode upon power-up MODE in interleave burst mode ZZ in normal operation mode These control pins can be connected to GNDQ or VCCQ to alter their power-up state

DESCRIPTION The ISSI IS61LV632A is a high-speed, low-power synchro-
nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium , 680X0 , and PowerPC microprocessors. It is organized
as 32,768 words by 32 bits, fabricated with ISSI's advanced

CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written. BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3 controls DQ17-DQ24, BW4 controls DQ25-DQ32, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written.

Bursts can be initiated with either ADSP Address Status Processor or ADSC Address Status Cache Controller input pins. Subsequent burst addresses can be generated internally by the IS61LV632A and controlled by the ADV burst address advance input pin.

Asynchronous signals include output enable OE , sleep mode input ZZ , clock CLK and burst mode input MODE . A HIGH input on the ZZ pin puts the SRAM in the power-down state. When ZZ is pulled LOW or no connect , the SRAM normally operates after three cycles of the wake-up period. A LOW input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ or no connect on MODE pin selects INTERLEAVED Burst.

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. Copyright 2001, Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. 1-800-379-4774
04/17/01

IS61LV632A

BLOCK DIAGRAM

CLK ADV ADSC ADSP
15 A14-A0

GW BWE BW4

CE1 CE2 CE3

ISSI

MODE

Q0 A0

BINARY

COUNTER

Q1 A1

ADDRESS REGISTER
32K x 32 MEMORY ARRAY
ORDERING INFORMATION Commercial Range 0°C to +70°C

Speed ns

Order Part Number

IS61LV632A-4TQ IS61LV632A-4PQ

IS61LV632A-5TQ IS61LV632A-5PQ

IS61LV632A-6TQ IS61LV632A-6PQ

IS61LV632A-7TQ IS61LV632A-7PQ

IS61LV632A-8TQ IS61LV632A-8PQ

Package

TQFP PQFP

TQFP PQFP

TQFP PQFP

TQFP PQFP

TQFP PQFP

Industrial Range to +85°C

Speed ns

Order Part Number

IS61LV632A-6TQI IS61LV632A-6PQI

IS61LV632A-7TQI IS61LV632A-7PQI

IS61LV632A-8TQI IS61LV632A-8PQI

Package

TQFP PQFP

TQFP PQFP

TQFP PQFP

ISSI

ISSI

Integrated Silicon Solution, Inc.
2231 Lawson Lane Santa Clara, CA 95054

Tel 1-800-379-4774 Fax 408 588-0806 E-mail:

Integrated Silicon Solution, Inc. 1-800-379-4774
04/17/01

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IS61LV632A-6TQI Datasheet file may be downloaded here without warranties.

Datasheet ID: IS61LV632A-6TQI 639316