IS45S16800B-7TLA1-TR

IS45S16800B-7TLA1-TR Datasheet

IS45S81600B IS45S16800B

Part	Datasheet
IS45S16800B-7TLA1-TR	IS45S16800B-7TLA1-TR (pdf)

Related Parts	Information
IS45S16800B-7TLA1	IS45S16800B-7TLA1

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IS45S81600B IS45S16800B 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM APRIL 2006 • Clock frequency 143, 100 MHz • Fully synchronous all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply IS45S81600B VDD VDDQ 3.3V 3.3V IS45S16800B 3.3V 3.3V • LVTTL interface • Programmable burst length 1, 2, 4, 8, full page • Programmable burst sequence Sequential/Interleave • Auto Refresh CBR • Self Refresh with programmable refresh periods • 4096 refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency 2, 3 clocks • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Automotive Temperature Range Option A 0oC to +70oC Option A1 -40oC to +85oC • Lead-free Availability OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized as follows. IS45S81600B 4M x8x4 Banks 54-pin TSOPII IS45S16800B 2M x16x4 Banks 54-pin TSOPII KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 Unit Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. 1-800-379-4774 04/14/06 IS45S81600B, IS45S16800B ISSI DEVICE OVERVIEW The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in BURST DEFINITION table. BURST DEFINITION Burst Length Full Page y Starting Column Address A1 A0 A2 A1 A0 n = A0-A7 location 0-y Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 Cn + 3, Cn + 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported Integrated Silicon Solution, Inc. 1-800-379-4774 IS45S81600B, IS45S16800B ISSI CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS Latency diagrams. The Allowable Operating Frequency table indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location nonburst accesses. CAS Latency Allowable Operating Frequency MHz Speed CAS Latency = 2 CAS Latency = 3 CAS LATENCY COMMAND DQ READ DOUT CAS Latency - 2 T0 CLK COMMAND READ ORDERING INFORMATION - VDD = 3.3V Automotive Range 0°C to 70°C Frequency 143 MHz Speed ns 7 Order Part No. IS45S81600B-7TA IS45S81600B-7TLA Package 54-Pin TSOPII 54-Pin TSOPII, Lead-free Frequency 143 MHz Speed ns 7 Order Part No. IS45S16800B-7TA IS45S16800B-7TLA Package 54-Pin TSOPII 54-Pin TSOPII, Lead-free Automotive Range -40°C to 85°C Frequency 143 MHz Speed ns 7 Order Part No. IS45S81600B-7TA1 IS45S81600B-7TLA1 Package 54-Pin TSOPII 54-Pin TSOPII, Lead-free Frequency 143 MHz Speed ns 7 Order Part No. IS45S16800B-7TA1 IS45S16800B-7TLA1 Package 54-Pin TSOPII 54-Pin TSOPII, Lead-free ISSI Integrated Silicon Solution, Inc. 1-800-379-4774 04/14/06 PACKAGING INFORMATION Plastic TSOP 86-Pin Package Code T Type II N/2+1 E1 E Notes Controlling dimension millimieters, unless otherwise specified. BSC = Basic lead spacing between centers. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. Formed leads shall be planar with respect to one another within inches at the seating plane. SEATING PLANE Plastic TSOP T - Type II Millimeters Inches Symbol Min Max Min Max

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IS45S81600B IS45S16800B
16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM

APRIL 2006
• Clock frequency 143, 100 MHz
• Fully synchronous all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge
• Power supply

IS45S81600B

VDD VDDQ 3.3V 3.3V

IS45S16800B
3.3V 3.3V
• LVTTL interface
• Programmable burst length 1, 2, 4, 8, full page
• Programmable burst sequence Sequential/Interleave
• Auto Refresh CBR
• Self Refresh with programmable refresh periods
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency 2, 3 clocks
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• Automotive Temperature Range

Option A 0oC to +70oC Option A1 -40oC to +85oC
• Lead-free Availability

OVERVIEW

ISSI's 128Mb Synchronous DRAM achieves high-speed
data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized as follows.

IS45S81600B 4M x8x4 Banks 54-pin TSOPII

IS45S16800B 2M x16x4 Banks 54-pin TSOPII

KEY TIMING PARAMETERS

Parameter

Clk Cycle Time CAS Latency = 3 CAS Latency = 2

Clk Frequency CAS Latency = 3 CAS Latency = 2

Access Time from Clock CAS Latency = 3 CAS Latency = 2

Unit

Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. 1-800-379-4774
04/14/06

IS45S81600B, IS45S16800B

ISSI

DEVICE OVERVIEW
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in BURST DEFINITION table.

BURST DEFINITION

Burst Length

Full Page y

Starting Column

Address

A1 A0

A2 A1 A0
n = A0-A7
location 0-y

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
0-1-2-3 1-0-3-2-3-0-1 3-2-1-0
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2 Cn + 3, Cn +
0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported

Integrated Silicon Solution, Inc. 1-800-379-4774

IS45S81600B, IS45S16800B

ISSI

CAS Latency

The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS Latency diagrams. The Allowable Operating Frequency table indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts.

Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location nonburst accesses.

CAS Latency

Allowable Operating Frequency MHz

Speed

CAS Latency = 2

CAS Latency = 3

CAS LATENCY

COMMAND DQ

READ

DOUT

CAS Latency - 2

T0 CLK

COMMAND READ
ORDERING INFORMATION - VDD = 3.3V Automotive Range 0°C to 70°C

Frequency 143 MHz

Speed ns 7

Order Part No.

IS45S81600B-7TA IS45S81600B-7TLA

Package
54-Pin TSOPII 54-Pin TSOPII, Lead-free

Frequency 143 MHz

Speed ns 7

Order Part No.

IS45S16800B-7TA IS45S16800B-7TLA

Package
54-Pin TSOPII 54-Pin TSOPII, Lead-free

Automotive Range -40°C to 85°C

Frequency 143 MHz

Speed ns 7

Order Part No.

IS45S81600B-7TA1 IS45S81600B-7TLA1

Package
54-Pin TSOPII 54-Pin TSOPII, Lead-free

Frequency 143 MHz

Speed ns 7

Order Part No.

IS45S16800B-7TA1 IS45S16800B-7TLA1

Package
54-Pin TSOPII 54-Pin TSOPII, Lead-free

ISSI

Integrated Silicon Solution, Inc. 1-800-379-4774
04/14/06

PACKAGING INFORMATION

Plastic TSOP 86-Pin Package Code T Type II

N/2+1 E1 E

Notes Controlling dimension millimieters,
unless otherwise specified. BSC = Basic lead spacing between
centers. Dimensions D and E1 do not include
mold flash protrusions and should be measured from the bottom of the package. Formed leads shall be planar with respect to one another within inches at the seating plane.

SEATING PLANE

Plastic TSOP T - Type II

Millimeters

Inches

Symbol Min Max Min Max

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Datasheet ID: IS45S16800B-7TLA1-TR 639302