IS42VM32400E-75BLI-TR

IS42VM32400E-75BLI-TR Datasheet

IS42VM81600E / IS42VM16800E / IS42VM32400E IS45VM81600E / IS45VM16800E / IS45VM32400E

Part	Datasheet
IS42VM32400E-75BLI-TR	IS42VM32400E-75BLI-TR (pdf)

Related Parts	Information
IS45VM16800E-75BLA2-TR	IS45VM16800E-75BLA2-TR
IS45VM16800E-75BLA1	IS45VM16800E-75BLA1
IS45VM16800E-75BLA2	IS45VM16800E-75BLA2
IS42VM16800E-75BLI	IS42VM16800E-75BLI
IS45VM16800E-75BLA1-TR	IS45VM16800E-75BLA1-TR
IS42VM32400E-75BLI	IS42VM32400E-75BLI
IS42VM16800E-75BLI-TR	IS42VM16800E-75BLI-TR

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IS42VM81600E / IS42VM16800E / IS42VM32400E IS45VM81600E / IS45VM16800E / IS45VM32400E 16Mx8, 8Mx16, 4Mx32 128Mb Mobile Synchronous DRAM FEATURES • Fully synchronous all signals referenced to a positive clock edge • Internal bank for hiding row access and pre- charge • Programmable CAS latency 2, 3 • Programmable Burst Length 1, 2, 4, 8, and Full Page • Programmable Burst Sequence • Sequential and Interleave • Auto Refresh CBR • TCSR Temperature Compensated Self Refresh • PASR Partial Arrays Self Refresh 1/16, 1/8, 1/4, 1/2, and Full • Deep Power Down Mode DPD • Driver Strength Control DS 1/4, 1/2, and Full OPTIONS • Configurations 16M x 8, 8M x 16, 4M x 32 • Power Supply IS42VMxxx Vdd/Vddq = V • Packages: x8 / x16 II 54 , BGA 54 [x16 only] x32 TSOP II 86 , BGA 90 • Temperature Range Commercial 0°C to +70°C Industrial ºC to 85 ºC Automotive, A1 ºC to 85 ºC Automotive, A2 ºC to 105 ºC JUNE 2011 ISSI's 128Mb Mobile Synchronous DRAM achieves highspeed data transfer using pipeline architecture. All input and output signals refer to the rising edge of the clock input. Both write and read accesses to the SDRAM are burst oriented. The 128Mb Mobile Synchronous DRAM is designed to minimize current consumption making it ideal for low-power applications. Both TSOP and BGA packages are offered, including industrial grade products. KEY TIMING PARAMETERS Parameter CLK Cycle Time CAS Latency = 3 CAS Latency = 2 CLK Frequency CAS Latency = 3 CAS Latency = 2 Access Time from CLK CAS Latency = 3 CAS Latency = 2 -10 Unit 10 ns 12 ns 100 Mhz 83 Mhz ADDRESSING TABLE Parameter Configuration Refresh Count Row Addressing Column Addressing Bank Addressing Precharge Addressing 16M x 8 4M x 8 x 4 banks 4K/64ms A0-A11 A0-A9 BA0, BA1 A10 8M x 16 2M x 16 x 4 banks 4K/64ms A0-A11 A0-A8 BA0, BA1 A10 4M x 32 1M x 32 x 4 banks 4K/64ms A0-A11 A0-A7 BA0, BA1 A10 Copyright 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that a. the risk of injury or damage has been minimized b. the user assume all such risks and c. potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. - 04/08/2011 IS42VM81600E / IS42VM16800E / IS42VM32400E IS45VM81600E / IS45VM16800E / IS45VM32400E ISSI’s 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 1.8V VDD/ VDDQ memory systems containing 134,271,728 bits. Internally configured as a quad-bank DRAM with a synchronous interface. The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVCMOS VDD = 1.8V compatible. The 128Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic columnaddress generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in BURST DEFINITION table. Burst Definition Burst Starting Column Order of Accesses Within a Burst Length Address Type = Sequential Type = Interleaved A 1 A 0 0-1-2-3 0-1-2-3 1-2-3-0 1-0-3-2 2-3-0-1 2-3-0-1 3-0-1-2 3-2-1-0 A2 A1 A0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Full n = A0-A7 x32 Page n = A0-A8 x16 y n = A0-A9 x8 location 0-y Cn, Cn + 1, Cn + 2 Cn + 3, Cn + Not Supported CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS Latency diagrams. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Integrated Silicon Solution, Inc. - 04/08/2011 Ordering Information Vdd = 1.8V Commercial Range 0°C to +70°C Configuration 8Mx16 4Mx32 Frequency MHz 133 Speed ns Order Part No. IS42VM16800E-75BL IS42VM32400E-75BL Industrial Range to 85ºC Configuration Frequency MHz Speed ns 16Mx8 8Mx16 4Mx32 Order Part No. IS42VM81600E-75TLI IS42VM16800E-75TLI IS42VM16800E-75BLI IS42VM32400E-75TLI IS42VM32400E-75BLI IS42VM32400E-10TLI IS42VM32400E-10BLI Package 54-Ball BGA, Lead-free 90-Ball BGA, Lead-free Package 54-pin TSOP II, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free Automotive Range A1 to 85ºC Configuration Frequency MHz Speed ns 8Mx16 4Mx32 Order Part No. IS45VM16800E-75BLA1 IS45VM32400E-75BLA1 Package 54-Ball BGA, Lead-free 90-Ball BGA, Lead-free Automotive Range A2 to 105ºC Configuration Frequency MHz Speed ns 8Mx16 4Mx32 Order Part No. IS45VM16800E-75BLA2 IS45VM32400E-75BLA2 Package 54-Ball BGA, Lead-free 90-Ball BGA, Lead-free Integrated Silicon Solution, Inc. - 04/08/2011 IS42VM81600E / IS42VM16800E / IS42VM32400E IS45VM81600E / IS45VM16800E / IS45VM32400E Integrated Silicon Solution, Inc. - 04/08/2011 IS42VM81600E / IS42VM16800E / IS42VM32400E IS45VM81600E / IS45VM16800E / IS45VM32400E 10/17/2007 Integrated Silicon Solution, Inc. - 04/08/2011 IS42VM81600E / IS42VM16800E / IS42VM32400E IS45VM81600E / IS45VM16800E / IS45VM32400E Integrated Silicon Solution, Inc. - 04/08/2011 NOTE : Controlling dimension mm Dimension D and E1 do not include mold protrusion Dimension b does not include dambar protrusion/intrusion.

PDF Datasheet Preview

IS42VM81600E / IS42VM16800E / IS42VM32400E IS45VM81600E / IS45VM16800E / IS45VM32400E
16Mx8, 8Mx16, 4Mx32 128Mb Mobile Synchronous DRAM

FEATURES
• Fully synchronous all signals referenced to a
positive clock edge
• Internal bank for hiding row access and pre-
charge
• Programmable CAS latency 2, 3
• Programmable Burst Length 1, 2, 4, 8, and Full

Page
• Programmable Burst Sequence
• Sequential and Interleave
• Auto Refresh CBR
• TCSR Temperature Compensated Self Refresh
• PASR Partial Arrays Self Refresh 1/16, 1/8,
1/4, 1/2, and Full
• Deep Power Down Mode DPD
• Driver Strength Control DS 1/4, 1/2, and Full

OPTIONS
• Configurations 16M x 8, 8M x 16, 4M x 32
• Power Supply

IS42VMxxx Vdd/Vddq = V
• Packages:
x8 / x16 II 54 , BGA 54 [x16 only] x32 TSOP II 86 , BGA 90
• Temperature Range Commercial 0°C to +70°C Industrial ºC to 85 ºC Automotive, A1 ºC to 85 ºC Automotive, A2 ºC to 105 ºC

JUNE 2011

ISSI's 128Mb Mobile Synchronous DRAM achieves highspeed data transfer using pipeline architecture. All input and output signals refer to the rising edge of the clock input. Both write and read accesses to the SDRAM are burst oriented. The 128Mb Mobile Synchronous DRAM is designed to minimize current consumption making it ideal for low-power applications. Both TSOP and BGA packages are offered, including industrial grade products.

KEY TIMING PARAMETERS

Parameter

CLK Cycle Time

CAS Latency = 3

CAS Latency = 2

CLK Frequency

CAS Latency = 3

CAS Latency = 2

Access Time from CLK

CAS Latency = 3

CAS Latency = 2
-10 Unit
10 ns 12 ns
100 Mhz 83 Mhz

ADDRESSING TABLE

Parameter

Configuration Refresh Count Row Addressing Column Addressing Bank Addressing Precharge Addressing
16M x 8
4M x 8 x 4 banks 4K/64ms A0-A11 A0-A9 BA0, BA1 A10
8M x 16
2M x 16 x 4 banks 4K/64ms A0-A11 A0-A8 BA0, BA1 A10
4M x 32
1M x 32 x 4 banks 4K/64ms A0-A11 A0-A7 BA0, BA1 A10

Copyright 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that a. the risk of injury or damage has been minimized b. the user assume all such risks and c. potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. -
04/08/2011

IS42VM81600E / IS42VM16800E / IS42VM32400E IS45VM81600E / IS45VM16800E / IS45VM32400E

ISSI’s 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 1.8V VDD/ VDDQ memory systems containing 134,271,728 bits. Internally configured as a quad-bank DRAM with a synchronous interface. The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVCMOS VDD = 1.8V compatible. The 128Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic columnaddress generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in BURST DEFINITION table.

Burst Definition

Burst Starting Column Order of Accesses Within a Burst

Length Address

Type = Sequential Type = Interleaved

A 1 A 0
0-1-2-3
0-1-2-3
1-2-3-0
1-0-3-2
2-3-0-1
2-3-0-1
3-0-1-2
3-2-1-0

A2 A1 A0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0

Full n = A0-A7 x32 Page n = A0-A8 x16
y n = A0-A9 x8 location 0-y

Cn, Cn + 1, Cn + 2 Cn + 3, Cn +

Not Supported

CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS Latency diagrams.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Operating Mode The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts.

Integrated Silicon Solution, Inc. -
04/08/2011
Ordering Information Vdd = 1.8V

Commercial Range 0°C to +70°C

Configuration 8Mx16 4Mx32

Frequency MHz 133

Speed ns

Order Part No. IS42VM16800E-75BL IS42VM32400E-75BL

Industrial Range to 85ºC

Configuration Frequency MHz Speed ns
16Mx8 8Mx16
4Mx32

Order Part No. IS42VM81600E-75TLI IS42VM16800E-75TLI IS42VM16800E-75BLI IS42VM32400E-75TLI IS42VM32400E-75BLI IS42VM32400E-10TLI IS42VM32400E-10BLI

Package 54-Ball BGA, Lead-free 90-Ball BGA, Lead-free

Package 54-pin TSOP II, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free

Automotive Range A1 to 85ºC

Configuration Frequency MHz Speed ns
8Mx16
4Mx32

Order Part No. IS45VM16800E-75BLA1 IS45VM32400E-75BLA1

Package 54-Ball BGA, Lead-free 90-Ball BGA, Lead-free

Automotive Range A2 to 105ºC

Configuration Frequency MHz Speed ns
8Mx16
4Mx32

Order Part No. IS45VM16800E-75BLA2 IS45VM32400E-75BLA2

Package 54-Ball BGA, Lead-free 90-Ball BGA, Lead-free

Integrated Silicon Solution, Inc. -
04/08/2011

IS42VM81600E / IS42VM16800E / IS42VM32400E IS45VM81600E / IS45VM16800E / IS45VM32400E

Integrated Silicon Solution, Inc. -
04/08/2011

IS42VM81600E / IS42VM16800E / IS42VM32400E IS45VM81600E / IS45VM16800E / IS45VM32400E
10/17/2007

Integrated Silicon Solution, Inc. -
04/08/2011

IS42VM81600E / IS42VM16800E / IS42VM32400E IS45VM81600E / IS45VM16800E / IS45VM32400E

Integrated Silicon Solution, Inc. -
04/08/2011

NOTE :

Controlling dimension mm

Dimension D and E1 do not include mold protrusion

Dimension b does not include dambar protrusion/intrusion.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IS42VM32400E-75BLI-TR Datasheet file may be downloaded here without warranties.

Datasheet ID: IS42VM32400E-75BLI-TR 639283