IS42SM16800E-75ETLI

IS42SM16800E-75ETLI Datasheet

IS42SM81600E / IS42SM16800E / IS42SM32400E IS42RM81600E / IS42RM16800E / IS42RM32400E

Part	Datasheet
IS42SM16800E-75ETLI	IS42SM16800E-75ETLI (pdf)

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IS42SM81600E / IS42SM16800E / IS42SM32400E IS42RM81600E / IS42RM16800E / IS42RM32400E 16Mx8, 8Mx16, 4Mx32 128Mb Mobile Synchronous DRAM FEATURES • Fully synchronous all signals referenced to a positive clock edge • Internal bank for hiding row access and pre- charge • Programmable CAS latency 2, 3 • Programmable Burst Length 1, 2, 4, 8, and Full Page • Programmable Burst Sequence • Sequential and Interleave • Auto Refresh CBR • TCSR Temperature Compensated Self Refresh • PASR Partial Arrays Self Refresh 1/16, 1/8, 1/4, 1/2, and Full • Deep Power Down Mode DPD • Driver Strength Control DS 1/4, 1/2, and Full OPTIONS • Configurations: Advanced Information FEBRUARY 2009 ISSI's 128Mb Mobile Synchronous DRAM achieves highspeed data transfer using pipeline architecture. All input and output signals refer to the rising edge of the clock input. Both write and read accesses to the SDRAM are burst oriented. The 128Mb Mobile Synchronous DRAM is designed to minimize current consumption making it ideal for low-power applications. Both TSOP and BGA packages are offered, including industrial grade products. KEY TIMING PARAMETERS Parameter CLK Cycle Time CAS Latency = 3 CAS Latency = 2 CLK Frequency CAS Latency = 3 CAS Latency = 2 Access Time from CLK CAS Latency = 3 CAS Latency = 2 -7 Unit 10 ns 143 Mhz 100 Mhz ADDRESSING TABLE Parameter Configuration Refresh Count Row Addressing Column Addressing Bank Addressing Precharge Addressing 16M x 8 4M x 8 x 4 banks 4K/64ms A0-A11 A0-A9 BA0, BA1 8M x 16 2M x 16 x 4 banks 4K/64ms A0-A11 A0-A8 BA0, BA1 4M x 32 1M x 32 x 4 banks 4K/64ms A0-A11 A0-A7 BA0, BA1 Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. - 12/22/08 IS42SM81600E / IS42SM16800E / IS42SM32400E IS42RM81600E / IS42RM16800E / IS42RM32400E ISSI’s 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V 2.5V VDD and 3.3V 2.5V VDDQ memory systems containing 134,271,728 bits. Internally configured as a quad-bank DRAM with a synchronous interface. The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL VDD = 3.3V or LVCMOS VDD = 2.5V compatible. The 128Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an Active command begins accesses, followed by a Read or Write command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed BA0, BA1 select the bank A0-A11 x8, x16 and x32 select the row . The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations, or full page, with a burst terminate option. Functional Block Diagram 8Mx16 CLK CKE CS RAS CAS WE The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in BURST DEFINITION table. Burst Definition Burst Starting Column Order of Accesses Within a Burst Length Address Type = Sequential Type = Interleaved A 1 A 0 0-1-2-3 0-1-2-3 1-2-3-0 1-0-3-2 2-3-0-1 2-3-0-1 3-0-1-2 3-2-1-0 A2 A1 A0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Full Page n = A0-A7 x32 n = A0-A8 x16 n = A0-A9 x8 location 0-y Cn, Cn + 1, Cn + 2 Cn + 3, Cn + Not Supported CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS Latency diagrams. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Integrated Silicon Solution, Inc. - Ordering Information Vdd = 3.3V Commercial Range 0°C to +70°C Configuration 16Mx8 8Mx16 4Mx32 Frequency MHz 143 166 Speed ns 7 6 Order Part No. IS42SM81600E-7TL IS42SM16800E-6TL IS42SM16800E-6BL IS42SM16800E-7TL IS42SM16800E-7BL IS42SM32400E-6TL IS42SM32400E-6BL IS42SM32400E-7TL IS42SM32400E-7BL Industrial Range to 85ºC Configuration 16Mx8 Frequency MHz Speed ns 8Mx16 4Mx32 Order Part No. IS42SM81600E-7TLI IS42SM16800E-6TLI IS42SM16800E-6BLI IS42SM16800E-7TLI IS42SM16800E-7BI IS42SM16800E-7BLI IS42SM32400E-6TLI IS42SM32400E-6BLI IS42SM32400E-7TLI IS42SM32400E-7BLI Contact Product Marketing for Leaded Parts Support. Package 54-pin TSOP II, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free Package 54-pin TSOP II, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA 54-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free Integrated Silicon Solution, Inc. - 12/22/08 IS42SM81600E / IS42SM16800E / IS42SM32400E IS42RM81600E / IS42RM16800E / IS42RM32400E Ordering Information Vdd = 2.5V Commercial Range 0°C to +70°C Configuration 16Mx8 8Mx16 4Mx32 Frequency MHz 143 166 Speed ns 7 6 Order Part No. IS42RM81600E-7TL IS42RM16800E-6TL IS42RM16800E-6BL IS42RM16800E-7TL IS42RM16800E-7BL IS42RM32400E-7TL IS42RM32400E-7BL Industrial Range to 85ºC Configuration 16Mx8 8Mx16 4Mx32 Frequency MHz 143 166 Speed ns 7 6 Order Part No. IS42RM81600E-7TLI IS42RM16800E-6TLI IS42RM16800E-6BLI IS42RM16800E-7TLI IS42RM16800E-7BLI IS42RM32400E-7TLI IS42RM32400E-7BLI Contact Product Marketing for Leaded Parts Support. Package 54-pin TSOP II, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free Package 54-pin TSOP II, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free Integrated Silicon Solution, Inc. - 12/22/08 12/22/08 Integrated Silicon Solution, Inc. - IS42SM81600E / IS42SM16800E / IS42SM32400E IS42RM81600E / IS42RM16800E / IS42RM32400E NOTE : Controlling dimension mm Dimension D and E1 do not include mold protrusion Dimension b does not include dambar protrusion/intrusion. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. 09/01/2006 IS42SM81600E / IS42SM16800E / IS42SM32400E IS42RM81600E / IS42RM16800E / IS42RM32400E 10/17/2007 Integrated Silicon Solution, Inc. - 12/22/08 12/22/08 Integrated Silicon Solution, Inc. - IS42SM81600E / IS42SM16800E / IS42SM32400E IS42RM81600E / IS42RM16800E / IS42RM32400E NOTE : Controlling dimension mm Dimension D and E1 do not include mold protrusion Dimension b does not include dambar protrusion/intrusion. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test.

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IS42SM81600E / IS42SM16800E / IS42SM32400E IS42RM81600E / IS42RM16800E / IS42RM32400E
16Mx8, 8Mx16, 4Mx32 128Mb Mobile Synchronous DRAM

FEATURES
• Fully synchronous all signals referenced to a
positive clock edge
• Internal bank for hiding row access and pre-
charge
• Programmable CAS latency 2, 3
• Programmable Burst Length 1, 2, 4, 8, and Full

Page
• Programmable Burst Sequence
• Sequential and Interleave
• Auto Refresh CBR
• TCSR Temperature Compensated Self Refresh
• PASR Partial Arrays Self Refresh 1/16, 1/8,
1/4, 1/2, and Full
• Deep Power Down Mode DPD
• Driver Strength Control DS 1/4, 1/2, and Full

OPTIONS
• Configurations:

Advanced Information FEBRUARY 2009

ISSI's 128Mb Mobile Synchronous DRAM achieves highspeed data transfer using pipeline architecture. All input and output signals refer to the rising edge of the clock input. Both write and read accesses to the SDRAM are burst oriented. The 128Mb Mobile Synchronous DRAM is designed to minimize current consumption making it ideal for low-power applications. Both TSOP and BGA packages are offered, including industrial grade products.

KEY TIMING PARAMETERS

Parameter

CLK Cycle Time

CAS Latency = 3

CAS Latency = 2

CLK Frequency

CAS Latency = 3

CAS Latency = 2

Access Time from CLK

CAS Latency = 3

CAS Latency = 2
-7 Unit
10 ns
143 Mhz 100 Mhz

ADDRESSING TABLE

Parameter Configuration Refresh Count Row Addressing Column Addressing Bank Addressing Precharge Addressing
16M x 8 4M x 8 x 4 banks
4K/64ms A0-A11 A0-A9 BA0, BA1
8M x 16 2M x 16 x 4 banks
4K/64ms A0-A11 A0-A8 BA0, BA1
4M x 32 1M x 32 x 4 banks
4K/64ms A0-A11 A0-A7 BA0, BA1

Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. -
12/22/08

IS42SM81600E / IS42SM16800E / IS42SM32400E IS42RM81600E / IS42RM16800E / IS42RM32400E

ISSI’s 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V 2.5V VDD and 3.3V 2.5V VDDQ memory systems containing 134,271,728 bits. Internally configured as a quad-bank DRAM with a synchronous interface. The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL VDD = 3.3V or LVCMOS VDD = 2.5V compatible. The 128Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access.

A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an Active command begins accesses, followed by a Read or Write command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed BA0, BA1 select the bank A0-A11 x8, x16 and x32 select the row . The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations, or full page, with a burst terminate option.

Functional Block Diagram 8Mx16

CLK CKE

CS RAS CAS WE
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in BURST DEFINITION table.

Burst Definition

Burst Starting Column Order of Accesses Within a Burst

Length Address

Type = Sequential Type = Interleaved

A 1 A 0
0-1-2-3
0-1-2-3
1-2-3-0
1-0-3-2
2-3-0-1
2-3-0-1
3-0-1-2
3-2-1-0

A2 A1 A0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0

Full Page
n = A0-A7 x32 n = A0-A8 x16 n = A0-A9 x8
location 0-y

Cn, Cn + 1, Cn + 2 Cn + 3, Cn +

Not Supported

CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in CAS Latency diagrams.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Operating Mode The normal operating mode is selected by setting M7 and M8 to zero the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts.

Integrated Silicon Solution, Inc. -
Ordering Information Vdd = 3.3V

Commercial Range 0°C to +70°C

Configuration 16Mx8 8Mx16
4Mx32

Frequency MHz 143 166

Speed ns 7 6

Order Part No. IS42SM81600E-7TL IS42SM16800E-6TL IS42SM16800E-6BL IS42SM16800E-7TL IS42SM16800E-7BL IS42SM32400E-6TL IS42SM32400E-6BL IS42SM32400E-7TL IS42SM32400E-7BL

Industrial Range to 85ºC

Configuration 16Mx8

Frequency MHz Speed ns
8Mx16
4Mx32

Order Part No. IS42SM81600E-7TLI IS42SM16800E-6TLI IS42SM16800E-6BLI IS42SM16800E-7TLI IS42SM16800E-7BI IS42SM16800E-7BLI IS42SM32400E-6TLI IS42SM32400E-6BLI IS42SM32400E-7TLI IS42SM32400E-7BLI
*Contact Product Marketing for Leaded Parts Support.

Package 54-pin TSOP II, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free

Package 54-pin TSOP II, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA 54-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free

Integrated Silicon Solution, Inc. -
12/22/08

IS42SM81600E / IS42SM16800E / IS42SM32400E IS42RM81600E / IS42RM16800E / IS42RM32400E
Ordering Information Vdd = 2.5V

Commercial Range 0°C to +70°C

Configuration 16Mx8 8Mx16
4Mx32

Frequency MHz 143 166

Speed ns 7 6

Order Part No. IS42RM81600E-7TL IS42RM16800E-6TL IS42RM16800E-6BL IS42RM16800E-7TL IS42RM16800E-7BL IS42RM32400E-7TL IS42RM32400E-7BL

Industrial Range to 85ºC

Configuration 16Mx8 8Mx16
4Mx32

Frequency MHz 143 166

Speed ns 7 6

Order Part No. IS42RM81600E-7TLI IS42RM16800E-6TLI IS42RM16800E-6BLI IS42RM16800E-7TLI IS42RM16800E-7BLI IS42RM32400E-7TLI IS42RM32400E-7BLI
*Contact Product Marketing for Leaded Parts Support.

Package 54-pin TSOP II, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free

Package 54-pin TSOP II, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 54-pin TSOP II, Lead-free 54-Ball BGA, Lead-free 86-pin TSOP II, Lead-free 90-Ball BGA, Lead-free

Integrated Silicon Solution, Inc. -
12/22/08
12/22/08

Integrated Silicon Solution, Inc. -

IS42SM81600E / IS42SM16800E / IS42SM32400E IS42RM81600E / IS42RM16800E / IS42RM32400E

NOTE :

Controlling dimension mm

Dimension D and E1 do not include mold protrusion

Dimension b does not include dambar protrusion/intrusion.

Formed leads shall be planar with respect to one another within 0.1mm
at the seating plane after final test.
09/01/2006

IS42SM81600E / IS42SM16800E / IS42SM32400E IS42RM81600E / IS42RM16800E / IS42RM32400E
10/17/2007

Integrated Silicon Solution, Inc. -
12/22/08
12/22/08

Integrated Silicon Solution, Inc. -

IS42SM81600E / IS42SM16800E / IS42SM32400E IS42RM81600E / IS42RM16800E / IS42RM32400E

NOTE :

Controlling dimension mm

Dimension D and E1 do not include mold protrusion

Dimension b does not include dambar protrusion/intrusion.

Formed leads shall be planar with respect to one another within 0.1mm
at the seating plane after final test.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IS42SM16800E-75ETLI Datasheet file may be downloaded here without warranties.

Datasheet ID: IS42SM16800E-75ETLI 639282