CA91C142D-33IE

CA91C142D-33IE Datasheet

Part Number CA91C142D-33CE CA91C142D-33CEV

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CA91C142D-33CE	CA91C142D-33CE
CA91C142D-33CEV	CA91C142D-33CEV
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Universe IID/IIBTM User Manual May 12, 2010 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone 800 345-7015 • 408 284-8200 • FAX 408 284-2775 Printed in U.S.A. 2009 Integrated Device Technology, Inc. GENERAL DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc. CODE DISCLAIMER Code examples provided by IDT are for illustrative purposes only and should not be relied upon for developing applications. Any use of the code examples below is completely at your own risk. IDT MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE NONINFRINGEMENT, QUALITY, SAFETY OR SUITABILITY OF THE CODE, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. FURTHER, IDT MAKES NO REPRESENTATIONS OR WARRANTIES AS TO THE TRUTH, ACCURACY OR COMPLETENESS OF ANY STATEMENTS, INFORMATION OR MATERIALS CONCERNING CODE EXAMPLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE. IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT, CONSEQUENTIAL, INCIDENTAL, INDIRECT, PUNITIVE OR SPECIAL DAMAGES, HOWEVER THEY MAY ARISE, AND EVEN IF IDT HAS BEEN PREVIOUSLY ADVISED ABOUT THE POSSIBILITY OF SUCH DAMAGES. The code examples also may be subject to United States export control laws and may be subject to the export or import laws of other countries and it is your responsibility to comply with any applicable laws or regulations. LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc. Contents Functional Overview 17 Overview 17 Universe II Features 18 Universe II Benefits 19 Universe II Typical Applications 19 Main Interfaces. 20 VMEbus Interface 22 PCI Bus Interface 22 Interrupter and Interrupt Handler 23 DMA Controller 24 VMEbus Interface 25 Overview 25 VMEbus Requester 25 Internal Arbitration for VMEbus Requests 25 Request Modes 26 VMEbus Release 27 Universe II as VMEbus Master 28 Addressing Capabilities 28 Data Transfer Capabilities 30 Cycle Terminations 31 Universe II as VMEbus Slave 32 Coupled Transfers 32 Posted Writes 33 Prefetched Block Reads 34 VMEbus Lock Commands ADOH Cycles 36 VMEbus Read-Modify-Write Cycles RMW Cycles 37 Register Accesses. 37 Location Monitors 38 Generating PCI Configuration Cycles 38 VMEbus Configuration 41 First Slot Detector 41 VMEbus Register Access at Power-up 41 Automatic Slot Identification 42 Auto Slot ID VME64 Specified 42 Auto-ID A Proprietary IDT Method 43 System Controller Functions 44 IACK Daisy-Chain Driver Module 45 VMEbus Time-out 45 Bus Isolation Mode BI-Mode 46 Integrated Device Technology Universe II User Manual May 12, 2010 Contents PCI Interface. 49 Overview 49 PCI Cycles 49 32-Bit Versus 64-Bit PCI 49 PCI Bus Request and Parking 50 Address Phase 50 Data Transfer 52 Termination Phase 52 Parity Checking 53 Universe II as PCI Master 53 Command Types 54 PCI Burst Transfers 55 Termination 55 Parity 56 Universe II as PCI Target. 57 Command Types 57 Data Transfer 57 Coupled Transfers 58 Posted Writes 60 Special Cycle Generator 61 Using the VOWN bit 64 Terminations 65 Slave Image Programming 67 Overview 67 VME Slave Image Programming. 67 VMEbus Fields 68 PCI Bus Fields 69 Control Fields 69 PCI Bus Target Images 70 PCI Bus Fields 71 VMEbus Fields 71 Control Fields 73 Special PCI Target Image 73 Registers Overview 75 Overview 75 Register Access from the PCI Bus. 76 PCI Configuration Access 76 Memory or I/O Access. 77 Locking the Register Block from the PCI bus. 78 Register Access from the VMEbus 79 VMEbus Register Access Image VRAI 79 CR/CSR Accesses 80 RMW and ADOH Register Access Cycles 81 Universe II User Manual May 12, 2010 Integrated Device Technology Contents Mailbox Registers 83 Semaphores 83 DMA Controller 85 Overview 85 DMA Registers. 85 Source and Destination Addresses 86 Non-incrementing DMA Mode 87 Transfer Size. 89 Transfer Data Width 89 DMA Command Packet Pointer. 90 DMA Control and Status 90 Direct Mode Operation 93 F. Ordering Information 373 F.1 Ordering Information 373 Integrated Device Technology Universe II User Manual May 12, 2010 Contents Universe II User Manual May 12, 2010 Integrated Device Technology Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42: Universe II Block Diagram 18 Universe II In Single Board Computer Application 20 Universe II Data Flow Diagram 21 VMEbus Slave Channel Dataflow. 32 Timing for Auto-ID Cycle. 44 PCI Bus Target Channel Dataflow 58 Register Fields for the Special Cycle Generator 62 Address Translation Mechanism for VMEbus to PCI Bus Transfers 69 Address Translation Mechanism for PCI Bus to VMEbus Transfers 72 Memory Mapping in the Special PCI Target Image 74 Universe II Control and Status Register Space 76 PCI Bus Access to UCSR as Memory or I/O Space 77 UCSR Access from the VMEbus Register Access Image. 80 UCSR Access in VMEbus CR/CSR Space 82 Direct Mode DMA transfers 94 Command Packet Structure and Linked List Operation 97 DMA Linked List Operation 98 Universe Interrupt Circuitry 110 STATUS/ID Provided by Universe II 115 Sources of Internal Interrupts 119 Reset Circuitry. 133 Resistor-Capacitor Circuit Ensuring Power-Up Reset Duration 134 Power-up Options Timing 139 UCSR Access Mechanisms 163 313 PBGA - Bottom View 333 313 PBGA - Top and Side View 334 Coupled Read Cycle - Universe II as VME Master 337 Several Coupled Read Cycles - Universe II as VME Master 337 Coupled Write Cycle - Universe II as VME Master 338 Several Non-Block Decoupled Writes - Universe II as VME Master. 340 BLT Decoupled Write - Universe II as VME Master 340 Coupled Read Cycle - Universe II as VME Slave 341 Coupled Write Cycle - Universe II as VME Slave bus parked at Universe II 342 Non-Block Decoupled Write Cycle - Universe II as VME Slave 343 BLT Decoupled Write Cycle - Universe II as VME Slave 344 MBLT Decoupled Write Cycle - Universe II as VME Slave 344 BLT Pre-fetched Read Cycle - Universe II as VME Slave 346 PCI Read Transactions During DMA Operation. 349 Multiple PCI Read Transactions During DMA Operation 349 Universe II Connections to the VMEbus Through TTL Buffers 364 Universe II Connections to the VMEbus Through TTL Buffers 365 Power-up Configuration Using Passive Pull-ups 368 Integrated Device Technology Universe II User Manual May 12, 2010 Figures Figure 43 Power-up Configuration Using Active Circuitry 368 Figure 44 Analog Isolation Scheme 371 Figure 45 Noise Filter Scheme 371 Universe II User Manual May 12, 2010 Integrated Device Technology Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42: VMEbus Address Modifier Codes 28 PCI Address Line Asserted as a Function of VA[15:11] 39 Command Type Encoding for Transfer Type 51 VMEbus Fields for VMEbus Slave Image. 67 PCI Bus Fields for VMEbus Slave Image 68 Control Fields for VMEbus Slave Image 68 PCI Bus Fields for the PCI Bus Target Image 70 VMEbus Fields for the PCI Bus Target Image 70 Control Fields for PCI Bus Target Image 71 PCI Bus Fields for the Special PCI Target Image 73 VMEbus Fields for the Special PCI Bus Target Image 73 Control Fields for the Special PCI Bus Target Image 73 Programming the VMEbus Register Access Image 79 VON Settings for Non-Inc Mode 88 DMA Interrupt Sources and Enable Bits 104 Source, Enabling, Mapping, and Status of PCI Interrupt Output. 112 Source, Enabling, Mapping, and Status of VMEbus Interrupt Outputs 114 Internal Interrupt Routing. 118 Hardware Reset Mechanisms 129 Software Reset Mechanism 130 Functions Affected by Reset Initiators. 132 Power-Up Options 135 VRAI Base Address Power-up Options 137 Manufacturing Pin Requirements for Normal Operating Mode 140 Test Mode Operation 141 VMEbus Signals. 144 PCI Bus Signals 147 Non-PCI Electrical Characteristics 153 AC/DC PCI Electrical Characteristics 154 Pin List and DC Characteristics for Universe II Signals 155 Operating Conditions 160 Absolute Maximum Ratings. 161 Power Dissipation 161 Universe II Register Map 164 Power-up Option Behavior of the VAS field in VRAI_CTL. 304 PCI Slave Channel Performance 352 VME Slave Channel Performance 352 DMA Channel Performance. 353 Ambient to Junction Thermal Impedance 357 Maximum Universe II Junction Temperature 357 Thermal Characteristics of Universe II 358 Mapping of 32-bit Little-Endian PCI Bus to 32-bit VMEbus 360 Integrated Device Technology Universe II User Manual May 12, 2010 Tables Table 43 Table 44 Table 45 Table 46 Table 47: Mapping of 32-bit Little-Endian PCI Bus to 64-bit VMEbus 361 VMEbus Signal Drive Strength Requirements 366 VMEbus Transceiver Requirements 366 Reset Signals 369 Standard Ordering Information 373 Universe II User Manual May 12, 2010 Integrated Device Technology About this Document This section discusses the following topics • “Scope” on page 13 • “Document Conventions” on page 13 • “Revision History” on page 15 Scope The Universe IID/IIB User Manual discusses the features, capabilities, and configuration requirements for the Universe II. It is intended for hardware and software engineers who are designing system interconnect applications with the device. Document Conventions This document uses the following conventions. Signal Notation Signals are either active high or active low. Active low signals are defined as true asserted when they are at a logic low. Similarly, active high signals are defined as true at a logic high. Signals are considered asserted when active and negated when inactive, irrespective of voltage levels. For voltage levels, the use of 0 indicates a low voltage while a 1 indicates a high voltage. For voltage levels, the use of 0 indicates a low voltage while a 1 indicates a high voltage. For voltage levels, the use of 0 indicates a low voltage while a 1 indicates a high voltage. Each signal that assumes a logic low state when asserted is followed by an underscore sign, For example, SIGNAL_ is asserted low to indicate an active low signal. Signals that are not followed by an underscore are asserted when they assume the logic high state. For example, SIGNAL is asserted high to indicate an active high signal. The asterisk sign “” is used in this manual to show that a signal is asserted low and that is used on the on the VMEbus backplane. For example, SIGNAL is asserted to low to indicate an active low signal on the VMEbus backplane. Integrated Device Technology Universe II User Manual May 12, 2010 About this Document Object Size Notation • A byte is an 8-bit object. • A word is a 16-bit object. • A doubleword Dword is a 32-bit object. • A quadword is a 64-bit 8 byte object. • A Kword is 1024 16-bit words. Numeric Notation • Hexadecimal numbers are denoted by the prefix 0x for example, 0x04 . • Binary numbers are denoted by the prefix 0b for example, 0b010 . • Registers that have multiple iterations are denoted by in their names where x is first register and address, and y is the last register and address. For example, indicates there are two versions of the register at different addresses REG0 and REG1. Symbols This symbol indicates a basic design concept or information considered helpful. This symbol indicates important configuration information or suggestions. This symbol indicates procedures or operating levels that may result in misuse or damage to the device. Document Status Information • Advance Contains information that is subject to change, and is available once prototypes are released to customers. • Formal Contains information about a final, customer-ready product, and is available once the product is released to production. Universe II User Manual May 12, 2010 Integrated Device Technology About this Document May 12, 2010, Formal This document fixed a number of minor typographical errors. No technical changes were made. October 2009, Formal This document was rebranded as IDT. No technical changes were made. June 2009, Formal There have been changes throughout the manual. August 2007, Formal There have been numerous edits throughout the manual. The formatting of the document has also been updated. November 2002, Formal Only aligned VMEbus transactions are generated, so if the requested PCI data beat has unaligned, or non-, byte enables, then it is broken into multiple aligned VMEbus transactions no wider than the programmed VMEbus data width. For example, consider a three-byte PCI data beat on a 32-bit PCI bus accessing a PCI target image with VDW set to 16 bits. The three-byte PCI data beat is broken into three aligned VMEbus cycles three single-byte cycle the ordering of the cycles depends on the arrangement of the byte enables in the PCI data beat . If in the above example the PCI target image has a VDW set to 8-bit, then the three-byte PCI data beat is broken into three single-byte VMEbus cycles. Universe II User Manual May 12, 2010 Integrated Device Technology VMEbus Interface > Universe II as VMEbus Master BLT/MBLT cycles are initiated on the VMEbus if the PCI target image has been programmed with this capacity see “PCI Bus Target Images” on page The length of the BLT/MBLT transactions on the VMEbus is determined by the initiating PCI transaction. For example, a single data beat PCI transaction queued in the TXFIFO results in a single data beat block transfer on the VMEbus. With the PWON field, the user can specify a transfer byte count that is queued from the TXFIFO before the VMEbus Master Interface relinquishes the VMEbus. The PWON field specifies the minimum tenure of the Universe II on the VMEbus. However, tenure is extended if the VOWN bit in the MAST_CTL register is set see “Using the VOWN bit” on page During DMA operations, the Universe II attempts block transfers to the maximum length permitted by the VMEbus specification 256 bytes for BLT, 2 Kbytes for MBLT and is limited by the VON counter see “DMA VMEbus Ownership” on page The Universe II provides indivisible transactions with the VMEbus lock commands and the VMEbus ownership bit see “VME Lock Access to VMEbus Resources” on page Cycle Terminations The Universe II accepts BERR* or DTACK* as cycle terminations from the VMEbus slave. It does not support RETRY. The assertion of BERR indicates that some type of system error occurred and the transaction did not complete properly. The assertion of BERR* during an IACK also causes the error to be logged. A VMEbus BERR* received by the Universe II during a coupled transaction is communicated to the PCI master as a Target-Abort. No information is logged if the Universe II receives BERR* in a coupled transaction. If an error occurs during a posted write to the VMEbus or during an IACK cycle, the Universe II uses the “VMEbus AM Code Error Log V_AMERR ” on page 307 to log the AM code of the transaction AMERR [5:0] , and the state of the IACK* signal IACK bit, to indicate whether the error occurred during an IACK cycle . The current transaction in the FIFO is purged. The V_AMERR register also records if multiple errors have occurred with the M_ERR bit , although the actual number of errors is not given. The error log is qualified by the value of the V_STAT bit. The address of the errored transaction is latched in the “VMEbus Address Error Log VAERR ” on page When the Universe II receives a VMEbus error during a posted write, it generates an interrupt on the VMEbus and/or PCI bus depending upon whether the VERR and LERR interrupts are enabled see “Interrupt Handling” on page DTACK* signals the successful completion of the transaction. Integrated Device Technology Universe II User Manual May 12, 2010 VMEbus Interface > Universe II as VMEbus Slave Universe II as VMEbus Slave This section describes the VMEbus Slave Channel and other aspects of the Universe II as VMEbus slave. The Universe II becomes VMEbus slave when one of its eight programmed slave images or register images are accessed by a VMEbus master. Depending upon the programming of the slave image, different possible transaction types can result see “VME Slave Image Programming” on page The Universe II cannot reflect a cycle on the VMEbus and access itself. For reads, the transaction can be coupled or prefetched. Write transactions can be coupled or posted. The type of read or write transaction allowed by the slave image depends on the programming of that particular VMEbus slave image see Figure 4 and “VME Slave Image Programming” on page To ensure sequential consistency, prefetched reads, coupled reads, and coupled write operations are only processed once all previously posted write operations have completed the RXFIFO is empty . Figure 4 VMEbus Slave Channel Dataflow PCI BUS MASTER INTERFACE COUPLED WRITE DATA RDFIFO PREFETCHED READ DATA COUPLED READ DATA VMEbus SLAVE INTERFACE POSTED WRITE DATA RXFIFO Incoming cycles from the VMEbus can have data widths of 8-bit, 16-bit, 32-bit, and 64-bit. Although the PCI bus supports only two port sizes 32-bit and 64-bit , the byte lanes on the PCI bus can be individually enabled, which allows each type of VMEbus transaction to be directly mapped to the PCI data bus. In order for a VMEbus slave image to respond to an incoming cycle, the PCI Master Interface must be enabled by setting the bit BM in the “PCI Configuration Space Control and Status Register PCI_CSR ” on page If data is queued in the VMEbus Slave Channel FIFO and the BM bit is cleared, the FIFO empties but no additional transfers are received. Coupled Transfers A coupled transfer means that no FIFO is involved in the transaction and handshakes are relayed directly through the Universe II. Coupled mode is the default setting for the VMEbus slave images. Coupled transfers only proceed once all posted write entries in the RXFIFO have completed see “Posted Writes” on page Universe II User Manual May 12, 2010 Integrated Device Technology VMEbus Interface > Universe II as VMEbus Slave A coupled cycle with multiple data beats such as block transfers on the VMEbus side is always mapped to single data beat transactions on the PCI bus, where each data beat on the VMEbus is mapped to a single data beat transaction on the PCI bus regardless of data beat size. No packing or unpacking is performed. The only exception to this is when a D64 VMEbus transaction is mapped to D32 on the PCI bus. The data width of the PCI bus depends on the programming of the VMEbus slave image 32-bit or 64-bit, see “VME Slave Image Programming” on page The Universe II enables the appropriate byte lanes on the PCI bus as required by the VMEbus transaction. For example, a VMEbus slave image programmed to generate 32-bit transactions on the PCI bus is accessed by a VMEbus D08 BLT read transaction prefetching is not enabled in this slave image . The transaction is mapped to single data beat 32-bit transfers on the PCI bus with only one byte lane enabled. Target-Retry from a PCI target is not communicated to the VMEbus master. PCI transactions terminated with Target-Abort or Master-Abort are terminated on the VMEbus with BERR. The Universe II sets the R_TA or R_MA bits in the “PCI Configuration Space Control and Status Register PCI_CSR ” on page 172 when it receives a Target-Abort or Master-Abort. Posted Writes A posted write involves the VMEbus master writing data into the Universe II’s RXFIFO, instead of directly to the PCI address. Write transactions from the VMEbus are processed as posted if the PWEN bit is set in the VMEbus slave image control register see “VME Slave Image Programming” on page If the bit is cleared default setting the transaction bypasses the FIFO and is performed as a coupled transfer. Incoming posted writes from the VMEbus are queued in the 64-entry deep RXFIFO. Each entry in the RXFIFO can contain 32 address bits, or 64 data bits. Each incoming VMEbus address phase, whether it is 16-bit, 24-bit, or 32-bit, constitutes a single entry in the RXFIFO and is followed by subsequent data entries. The address entry contains the translated PCI address space and command information mapping relevant to the particular VMEbus slave image that has been accessed see “VME Slave Image Programming” on page For this reason, any reprogramming of VMEbus slave image attributes are only reflected in RXFIFO entries queued after the reprogramming. Transactions queued before the re-programming are delivered to the PCI bus with the VMEbus slave image attributes that were in use before the reprogramming. The RXFIFO is the same structure as the RDFIFO. The different names are used for the FIFO’s two roles. In each FIFO, only one role, either the RXFIFO or the RDFIFO, can used at one time. FIFO Entries The PCI Bus Interface of the Universe II operates as a PCI compliant port with a 64-bit multiplexed address/data bus. The Universe II PCI Bus Interface is configured as little-endian using address invariant translation when mapping between the VMEbus and the PCI bus. Address invariant translation preserves the byte ordering of a data structure in a little-endian memory map and a big-endian memory map see “Endian Mapping” on page 359 and the PCI Specification . The Universe II has all the PCI signals described in the PCI Specification with the exception of SBO_ and SDONE. These pins are exception because the Universe II does not provide cache support. Universe II PCI cycles are synchronous, meaning that bus and control input signals are externally synchronized to the PCI clock CLK . PCI cycles are divided into the following phases Request Address Data transfer Cycle termination 32-Bit Versus 64-Bit PCI The Universe II is configured with a 32-bit or 64-bit PCI data bus at power-up see “PCI Bus Width” on page Integrated Device Technology Universe II User Manual May 12, 2010 PCI Interface > PCI Cycles Each of the Universe II’s VMEbus slave images can be programmed so that VMEbus transactions are mapped to a 64-bit data bus on the PCI Interface through the LD64EN bit, in the “DMA Transfer Control Register DCTL ” on page If the VMEbus slave image is programmed with a 64-bit PCI bus data width and Universe II is powered-up in a 64-bit PCI environment, the Universe II asserts REQ64_ during the address phase of the PCI transaction. REQ64_ is asserted if LD64EN is set in a 64-bit PCI system independent of whether the Universe II has a full 64-bit transfer. This can result in a performance degradation because of the extra clocks required to assert REQ64_ and to sample ACK64_. Also, there can be some performance degradation when accessing 32-bit targets with LD64EN set. Do not set the LD64EN bit unless there are 64-bit targets in the slave image window. If the VMEbus slave images are not programmed for a 64-bit wide PCI data bus, then the Universe operates transparently in a 32-bit PCI environment. Independent of the setting of the LD64EN bit, the Universe II never attempts a 64-bit cycle on the PCI bus if it is powered-up as a 32-bit device. PCI Bus Request and Parking The Universe II supports bus parking. If the Universe II requires the PCI bus it asserts REQ_ only if its GNT_ is not currently asserted. When the PCI Master Module is ready to begin a transaction and its GNT_ is asserted, the transfer begins immediately. This eliminates a possible one clock cycle delay before beginning a transaction on the PCI bus which would exist if the Universe II did not implement bus parking. Refer to the PCI Specification for more information Address Phase PCI transactions are initiated by asserting FRAME_ and driving address and command information onto the bus. In the VMEbus Slave Channel, the Universe II calculates the address for the PCI transaction by adding a translation offset to the VMEbus address see “Universe II as VMEbus Slave” on page Universe II User Manual May 12, 2010 Integrated Device Technology PCI Interface > PCI Cycles The command signals on the C/BE_ lines contain information about Memory space, cycle type and whether the transaction is read or write. Table 3 shows the PCI command type encoding implemented with the Universe II. Table 3 Command Type Encoding for Transfer Type C/BE_ [3:0] for PCI, C/BE_ [7:4] for non-multiplexed 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Command Type Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Memory Read Memory Write Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate Universe II Capability N/A N/A Target/Master Target/Master N/A N/A Target/Master Target/Master N/A N/A Target/Master Target/Master See “Memory Read Types” on page 51 N/A See “Memory Read Types” on page 51 See “Memory Read Types” on page 51 Memory Read Types Memory Read Multiple and Memory Read Line transactions are aliased to Memory Read transactions when the Universe II is accessed as a PCI target with these commands. Likewise, Memory Write and Invalidate is aliased to Memory Write. As a PCI master, the Universe II can generate Memory Read Multiple but not Memory Read Line. Integrated Device Technology Universe II User Manual May 12, 2010 PCI Interface > PCI Cycles PCI targets must assert DEVSEL_ if they have decoded the access. During a Configuration cycle, the target is selected by its particular ID Select IDSEL . If a target does not respond with DEVSEL_ within six clocks, a Master-abort is generated. The role of configuration cycles is described in the PCI Specification. Data Transfer Acknowledgment of a data phase occurs on the first rising clock edge after both IRDY_ and TRDY_ are asserted by the master and target, respectively. REQ64_ can be driven during the address phase to indicate that the master wishes to initiate a 64-bit transaction. The PCI target asserts ACK64_ if it is able to respond to the 64-bit transaction. Wait cycles are introduced by either the master or the target by de-asserting IRDY_ or TRDY_. For write cycles, data is valid on the first rising edge after IRDY_ is asserted. Data is acknowledged by the target on the first rising edge with TRDY_ asserted. For read cycles, data is transferred and acknowledged on first rising edge with both IRDY_ and TRDY_ asserted. A single data transfer cycle is repeated every time IRDY_ and TRDY_ are both asserted. The transaction only enters the termination phase when FRAME_ is de-asserted master-initiated termination or if STOP_ is asserted target-initiated . When both FRAME_ and IRDY_ are de-asserted final data phase is complete , the bus is defined as idle. Termination Phase The Universe II does not apply PCI Specification transaction ordering requirements to the DMA Controller. Reads and writes through the DMA Controller can occur independently of the other channels. ADOH cycles and RMW cycles through the VMEbus Slave Channel do impact on the DMA Channel. Once an external VMEbus master locks the PCI bus, the DMA Controller does not perform transfers on the PCI bus until the Universe II is unlocked see “VMEbus Lock Commands ADOH Cycles ” on page When an external VMEbus Master begins a RMW cycle, at some point a read cycle appears on the PCI bus. During the time between when the read cycle occurs on the PCI bus and when the associated write cycle occurs on the PCI bus, no DMA transfers occurs on the PCI bus see “VMEbus Read-Modify-Write Cycles RMW Cycles ” on page If the PCI Target Channel locks the VMEbus using VOWN, no DMA transfers takes place on the VMEbus see “Using the VOWN bit” on page DMA Error Handling This section describes how the Universe II responds to errors involving the DMA, and how the user can recover from them. The software source of a DMA error is a protocol, and the hardware source of a DMA error is a VMEbus error, or PCI bus Target-Abort or Master-Abort. DMA Software Response to Error While the DMA is operating normally, the ACT bit in the “DMA General Control/Status Register DGCS ” on page Once the DMA has terminated, it clears this bit, and sets one of six status bits in the same register. The DONE bit will be set if the DMA completed all its programmed operations normally. If the DMA is interrupted, either the STOP or HALT bits are set. If an error has occurred, one of the remaining three bits, LERR, VERR, or P_ERR, is set. All six forms of DMA terminations can be optionally set to generate a DMA interrupt by setting the appropriate enable bit in the DGCS register see “DMA Interrupts” on page • LERR is set if the DMA encounters an error on the PCI bus either a Master-Abort or Target-Abort Bits in the “PCI Configuration Space Control and Status Register PCI_CSR ” on page 172 indicate which of these conditions caused the error. Integrated Device Technology Universe II User Manual May 12, 2010 DMA Controller > DMA Error Handling • VERR is set if the DMA encounters a bus error on the VMEbus. This is through a detected assertion of BERR during a DMA cycle. • P_ERR is set if the GO bit in the DGCS register is set to start the DMA, and the DMA has been improperly programmed either because the BM bit in the PCI_CSR disables PCI bus mastership, or the source and destination start addresses are not aligned see “Source and Destination Addresses” on page Whether the error occurs on the destination or source bus, the DMA_CTL register contains the attributes relevant to the particular DMA transaction. The DTBC register provides the number of bytes remaining to transfer on the PCI side. The DTBC register contains valid values after an error. The DLA and DVA registers should not be used for error recovery. DMA Hardware Response to Error When the error condition VMEbus Error, Target-Abort, or Master-Abort occurs on the source bus while the DMA is reading from the source bus, the DMA stops reading from the source bus. Any data previously queued within the DMAFIFO is written to the destination bus. Once the DMAFIFO empties, the error status bit is set and the DMA generates an interrupt if enabled by INT_LERR or INT_VERR in the DGCS “DMA Interrupts” on page When the error condition VMEbus Error, Target-Abort, or Master-Abort occurs on the destination bus while the DMA is writing data to the destination bus, the DMA stops writing to the destination bus, and it also stops reading from the source bus. The error bit in the DGCS register is set and an interrupt asserted if enabled . Interrupt Generation During Bus Errors To generate an interrupt from a DMA error, there are two bits in the DGCS register, and one bit each in the VINT_EN and LINT_EN registers. In the DGCS register the INT_LERR bit enables the DMA to generate an interrupt to the Interrupt Channel after encountering an error on the PCI bus. The INT_VERR enables the DMA to generate an interrupt to the Interrupt Channel upon encountering an error on the VMEbus. Upon reaching the Interrupt Channel, all DMA interrupts can be routed to either the PCI bus or VMEbus by setting the appropriate bit in the enable registers. All DMA sources of interrupts Done, Stopped, Halted, VMEbus Error, and PCI Error constitute a single interrupt into the Interrupt Channel. Resuming DMA Transfers When a DMA error occurs on the source or destination bus , the status bits must be read in order to determine the source of the error. If it is possible to resume the transfer, the transfer should be resumed at the address that was in place up to 256 bytes from the current byte count. The original addresses DLA and DVA are required in order to resume the transfer at the appropriate location. However, the values in the DLA and the DVA registers should not be used to reprogram the DMA, because they are not valid once the DMA begins. In direct mode, it is the user’s responsibility to record the original state of the DVA and DLA registers for error recovery. In Linked-List mode, the user can refer to the current Command Packet stored on the PCI bus whose location is specified by the DCPP register for the location of the DVA and DLA information. Universe II User Manual May 12, 2010 Integrated Device Technology DMA Controller > DMA Error Handling The DTBC register contains the number of bytes remaining to transfer on the source side. The Universe II does not store a count of bytes to transfer on the destination side. If the error occurred on the source side, then the location of the error is simply the latest source address plus the byte count. If the error occurred on the destination side, then one cannot infer specifically where the error occurred, because the byte count only refers to the number of data queued from the source, not what has been written to the destination. In this case, the error will have occurred up to 256 bytes before the original address plus the byte count. Given this background, the following procedure can be implemented to recover from errors. Read the value contained in the DTBC register. Read the record of the DVA and DLA that is stored on the PCI bus or elsewhere not the value stored in the Universe II registers of the same name . If the difference between the value contained in the DTBC register and the original value is less than 512 bytes the FIFO depth of the Universe II , reprogram all the DMA registers with their original values. If the difference between the value contained in the DTBC register and the original value is greater than 512 bytes the FIFO depth of the Universe II , add 512 bytes to the value contained in the DTBC register. Add the difference between the original value in the DTBC and the new value in the DTBC register to the original value in the DLA register. Add the difference between the original value in the DTBC and the new value in the DTBC register to the original value in the DVA register. Clear the status flags. Restart the DMA see “DMA Initiation” on page Integrated Device Technology Universe II User Manual May 12, 2010 DMA Controller > DMA Error Handling Universe II User Manual May 12, 2010 Integrated Device Technology Interrupt Generation and Handling Universe II registers have little-endian byte-ordering. Figure 24 below summarizes the supported register access mechanisms. Figure 24 UCSR Access Mechanisms VMEbus Configuration and Status Registers VCSR UNIVERSE DEVICE SPECIFIC REGISTERS UDSR 4 Kbytes UCSR Space PCI CONFIGURATION SPACE PCICS Integrated Device Technology Universe II User Manual May 12, 2010 Registers > Register Map Bits listed as reserved must be programmed with a value of Reserved bits always read a value of zero. Register Map Table 34 lists the Universe II registers by address offset. Table 34 Universe II Register Map Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018-0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040-0x0FF 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C Register “PCI Configuration Space ID Register PCI_ID ” on page 171 “PCI Configuration Space Control and Status Register PCI_CSR ” on page 172 “PCI Configuration Class Register PCI_CLASS ” on page 176 “PCI Configuration Miscellaneous 0 Register PCI_MISC0 ” on page 177 “PCI Configuration Base Address Register PCI_BS0 ” on page 178 “PCI Configuration Base Address 1 Register PCI_BS1 ” on page 179 PCI Unimplemented PCI Reserved PCI Reserved PCI Unimplemented PCI Reserved PCI Reserved “PCI Configuration Miscellaneous 1 Register PCI_MISC1 ” on page 180 PCI Unimplemented “PCI Target Image 0 Control LSI0_CTL ” on page 181 “PCI Target Image 0 Base Address Register LSI0_BS ” on page 183 “PCI Target Image 0 Bound Address Register LSI0_BD ” on page 184 “PCI Target Image 0 Translation Offset LSI0_TO ” on page 185 Reserved “PCI Target Image 1 Control LSI1_CTL ” on page 186 “PCI Target Image 1 Base Address Register LSI1_BS ” on page 188 “PCI Target Image 1 Bound Address Register LSI1_BD ” on page 189 Name PCI_ID PCI_CSR PCI_CLASS PCI_MISC0 PCI_BS0 PCI_BS1 PCI_MISC1 LSI0_CTL LSI0_BS LSI0_BD LSI0_TO LSI1_CTL LSI1_BS LSI1_BD Universe II User Manual May 12, 2010 Integrated Device Technology Registers > Register Map Table 34 Universe II Register Map Continued Offset 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C 0x140 0x144 0x148 0x14C-0x16C 0x170 0x174 0x178 0x17C 0x180 0x184 0x188 0x18C 0x190 0x194-0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 Register “PCI Target Image 1 Translation Offset LSI1_TO ” on page 190 Reserved “PCI Target Image 2 Control LSI2_CTL ” on page 191 “PCI Target Image 2 Base Address Register LSI2_BS ” on page 193 “PCI Target Image 2 Bound Address Register LSI2_BD ” on page 194 “PCI Target Image 2 Translation Offset LSI2_TO ” on page 195 Reserved “PCI Target Image 3 Control LSI3_CTL ” on page 196 “PCI Target Image 3 Base Address Register LSI3_BS ” on page 198 “PCI Target Image 3 Bound Address Register LSI3_BD ” on page 199 “PCI Target Image 3 Translation Offset LSI3_TO ” on page 200 Reserved “Special Cycle Control Register SCYC_CTL ” on page 201 “Special Cycle PCI Bus Address Register SCYC_ADDR ” on page 202 “Special Cycle Swap/Compare Enable Register SCYC_EN ” on page 203 “Special Cycle Compare Data Register SCYC_CMP ” on page 204 “Special Cycle Swap Data Register SCYC_SWP ” on page 205 “PCI Miscellaneous Register LMISC ” on page 206 “Special PCI Target Image SLSI ” on page 208 “PCI Command Error Log Register L_CMDERR ” on page 210 “PCI Address Error Log LAERR ” on page 211 Reserved “PCI Target Image 4 Control Register LSI4_CTL ” on page 212 “PCI Target Image 4 Base Address Register LSI4_BS ” on page 214 “PCI Target Image 4 Bound Address Register LSI4_BD ” on page 215 “PCI Target Image 4 Translation Offset LSI4_TO ” on page 216 Reserved Name LSI1_TO LSI2_CTL LSI2_BS LSI2_BD LSI2_TO LSI3_CTL LSI3_BS LSI3_BD LSI3_TO SCYC_CTL SCYC_ADDR SCYC_EN SCYC_CMP SCYC_SWP LMISC SLSI L_CMDERR LAERR LSI4_CTL LSI4_BS LSI4_BD LSI4_TO Integrated Device Technology Universe II User Manual May 12, 2010 Registers > Register Map The Universe II always performs Address Invariant translation between the PCI and VMEbus ports. Address Invariant mapping preserves the byte ordering of a data structure in a little-endian memory map and a big-endian memory map. Little-endian Mode Table 42 shows the byte lane swapping and address translation between a 32-bit little-endian PCI bus and the VMEbus for the address invariant translation scheme. Integrated Device Technology Universe II User Manual May 12, 2010 D. Endian Mapping > Little-endian Mode Table 42 Mapping of 32-bit Little-Endian PCI Bus to 32-bit VMEbus PCI Bus Byte Enables Address VMEbus Byte Lane Mapping DS1 DS0 A1 LW D0-D7 D8-D15 D8-D15 D0-D7 D16-D23 D8-D15 D24-D31 D0-D7 D0-D7 D8-D15 D8-D15 D0-D7 D8-D15 D16-D23 D16-D23 D8-D15 D16-D23 D8-D15 D24-D31 D0-D7 D0-D7 D24-D31 D8-D15 D16-D23 D16-D23 D8-D15 D8-D15 D16-D23 F. Ordering Information This appendix discusses Universe II’s ordering information. Ordering Information IDT products are designated by a product code. When ordering, refer to products by their full code. Table 47 details the available part numbers. Table 47 Standard Ordering Information Part Number CA91C142D-33CE CA91C142D-33CEV PCI Frequency 33 MHz 33 MHz CA91C142D-33IE CA91C142D-33IEV 33 MHz 33 MHz CA91C142D-25EE 25 MHz Voltage 5V Temperature Package Commercial 0° to 70°C PBGA Commercial 0° to 70°C PBGA RoHS/Green Industrial -40° to 85°C PBGA Industrial PBGA -40° to 85°C RoHS/Green Extended -55° to 125°C PBGA Integrated Device Technology Universe II User Manual May 12, 2010 F. Ordering Information > Ordering Information The IDT “Tsi” part numbering system is explained as follows. Tsi NNN N - SS S E P G Z# IDT product identifier Product number Operating frequency Operating environment Package type RoHS/Green compliance Prototype version status • Indicates optional characters. • Tsi IDT “Tsi” product identifier. • NNNN Product number may be three or four digits . • SS S Maximum operating frequency or data transfer rate of the fastest interface. For operating frequency numbers, M and G represent MHz and GHz. For transfer rate numbers, M and G represent Mbps and Gbps. • E Operating environment in which the product is guaranteed. This code may be one of the following characters C - Commercial temperature range 0 to +70°C I - Industrial temperature range -40 to +85°C E - Extended temperature range -55 to +125°C • P The Package type of the product B - Ceramic ball grid array CBGA E, L, J, and K - Plastic ball grid array PBGA G - Ceramic pin grid array CPGA M - Small outline integrated circuit SOIC Q - Plastic quad flatpack QFP Universe II User Manual May 12, 2010 Integrated Device Technology F. Ordering Information > Ordering Information • G IDT “Tsi” products fit into three RoHS-compliance categories: Y - RoHS Compliant 6of6 These products contain none of the six restricted substances above the limits set in the EU Directive 2002/95/EC. Y - RoHS Compliant Flip Chip These products contain only one of the six restricted substances Lead Pb . These flip-chip products are RoHS compliant through the Lead exemption for Flip Chip technology, Commission Decision 2005/747/EC, which allows Lead in solders to complete a viable electrical connection between semiconductor die and carrier within integrated circuit Flip Chip packages. V - RoHS Compliant/Green - These products follow the above definitions for RoHS Compliance and meet JIG Joint Industry Guide Level B requirements for Brominated Flame Retardants other than PBBs and PBDEs . Integrated Device Technology Universe II User Manual May 12, 2010 F. Ordering Information > Ordering Information Universe II User Manual May 12, 2010 Integrated Device Technology CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support email phone 408-360-1538 Document May 12, 2010 DISCLAIMER Integrated Device Technology, Inc. IDT and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. 2010 Integrated Device Technology, Inc *Notice The information in this document is subject to change without notice May 2010

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Universe IID/IIBTM User Manual

May 12, 2010
6024 Silver Creek Valley Road, San Jose, California 95138 Telephone 800 345-7015
• 408 284-8200
• FAX 408 284-2775

Printed in U.S.A. 2009 Integrated Device Technology, Inc.

GENERAL DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

CODE DISCLAIMER Code examples provided by IDT are for illustrative purposes only and should not be relied upon for developing applications. Any use of the code examples below is completely at your own risk. IDT MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE NONINFRINGEMENT, QUALITY, SAFETY OR SUITABILITY OF THE CODE, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. FURTHER, IDT MAKES NO REPRESENTATIONS OR WARRANTIES AS TO THE TRUTH, ACCURACY OR COMPLETENESS OF ANY STATEMENTS, INFORMATION OR MATERIALS CONCERNING CODE EXAMPLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE. IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT, CONSEQUENTIAL, INCIDENTAL, INDIRECT, PUNITIVE OR SPECIAL DAMAGES, HOWEVER THEY MAY ARISE, AND EVEN IF IDT HAS BEEN PREVIOUSLY ADVISED ABOUT THE POSSIBILITY OF SUCH DAMAGES. The code examples also may be subject to United States export control laws and may be subject to the export or import laws of other countries and it is your responsibility to comply with any applicable laws or regulations.

LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.

Contents

Functional Overview 17

Overview 17 Universe II Features 18 Universe II Benefits 19 Universe II Typical Applications 19

Main Interfaces. 20 VMEbus Interface 22 PCI Bus Interface 22 Interrupter and Interrupt Handler 23 DMA Controller 24

VMEbus Interface 25

Overview 25 VMEbus Requester 25

Internal Arbitration for VMEbus Requests 25 Request Modes 26 VMEbus Release 27 Universe II as VMEbus Master 28 Addressing Capabilities 28 Data Transfer Capabilities 30 Cycle Terminations 31 Universe II as VMEbus Slave 32 Coupled Transfers 32 Posted Writes 33 Prefetched Block Reads 34 VMEbus Lock Commands ADOH Cycles 36 VMEbus Read-Modify-Write Cycles RMW Cycles 37 Register Accesses. 37 Location Monitors 38 Generating PCI Configuration Cycles 38 VMEbus Configuration 41 First Slot Detector 41 VMEbus Register Access at Power-up 41 Automatic Slot Identification 42 Auto Slot ID VME64 Specified 42 Auto-ID A Proprietary IDT Method 43 System Controller Functions 44 IACK Daisy-Chain Driver Module 45 VMEbus Time-out 45 Bus Isolation Mode BI-Mode 46

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Contents

PCI Interface. 49

Overview 49 PCI Cycles 49
32-Bit Versus 64-Bit PCI 49 PCI Bus Request and Parking 50 Address Phase 50 Data Transfer 52 Termination Phase 52 Parity Checking 53 Universe II as PCI Master 53 Command Types 54 PCI Burst Transfers 55 Termination 55 Parity 56 Universe II as PCI Target. 57 Command Types 57 Data Transfer 57 Coupled Transfers 58 Posted Writes 60 Special Cycle Generator 61 Using the VOWN bit 64 Terminations 65

Slave Image Programming 67

Overview 67 VME Slave Image Programming. 67

VMEbus Fields 68 PCI Bus Fields 69 Control Fields 69 PCI Bus Target Images 70 PCI Bus Fields 71 VMEbus Fields 71 Control Fields 73 Special PCI Target Image 73

Registers Overview 75

Overview 75 Register Access from the PCI Bus. 76

PCI Configuration Access 76 Memory or I/O Access. 77 Locking the Register Block from the PCI bus. 78 Register Access from the VMEbus 79 VMEbus Register Access Image VRAI 79 CR/CSR Accesses 80 RMW and ADOH Register Access Cycles 81

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Contents

Mailbox Registers 83 Semaphores 83

DMA Controller 85

Overview 85

DMA Registers. 85

Source and Destination Addresses 86

Non-incrementing DMA Mode 87

Transfer Size. 89

Transfer Data Width 89

DMA Command Packet Pointer. 90

DMA Control and Status 90

Direct Mode Operation 93
F. Ordering Information 373
F.1 Ordering Information 373

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Contents

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Integrated Device Technology

Figures

Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42:

Universe II Block Diagram 18 Universe II In Single Board Computer Application 20 Universe II Data Flow Diagram 21 VMEbus Slave Channel Dataflow. 32 Timing for Auto-ID Cycle. 44 PCI Bus Target Channel Dataflow 58 Register Fields for the Special Cycle Generator 62 Address Translation Mechanism for VMEbus to PCI Bus Transfers 69 Address Translation Mechanism for PCI Bus to VMEbus Transfers 72 Memory Mapping in the Special PCI Target Image 74 Universe II Control and Status Register Space 76 PCI Bus Access to UCSR as Memory or I/O Space 77 UCSR Access from the VMEbus Register Access Image. 80 UCSR Access in VMEbus CR/CSR Space 82 Direct Mode DMA transfers 94 Command Packet Structure and Linked List Operation 97 DMA Linked List Operation 98 Universe Interrupt Circuitry 110 STATUS/ID Provided by Universe II 115 Sources of Internal Interrupts 119 Reset Circuitry. 133 Resistor-Capacitor Circuit Ensuring Power-Up Reset Duration 134 Power-up Options Timing 139 UCSR Access Mechanisms 163 313 PBGA - Bottom View 333 313 PBGA - Top and Side View 334 Coupled Read Cycle - Universe II as VME Master 337 Several Coupled Read Cycles - Universe II as VME Master 337 Coupled Write Cycle - Universe II as VME Master 338 Several Non-Block Decoupled Writes - Universe II as VME Master. 340 BLT Decoupled Write - Universe II as VME Master 340 Coupled Read Cycle - Universe II as VME Slave 341 Coupled Write Cycle - Universe II as VME Slave bus parked at Universe II 342 Non-Block Decoupled Write Cycle - Universe II as VME Slave 343 BLT Decoupled Write Cycle - Universe II as VME Slave 344 MBLT Decoupled Write Cycle - Universe II as VME Slave 344 BLT Pre-fetched Read Cycle - Universe II as VME Slave 346 PCI Read Transactions During DMA Operation. 349 Multiple PCI Read Transactions During DMA Operation 349 Universe II Connections to the VMEbus Through TTL Buffers 364 Universe II Connections to the VMEbus Through TTL Buffers 365 Power-up Configuration Using Passive Pull-ups 368

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Figures

Figure 43 Power-up Configuration Using Active Circuitry 368 Figure 44 Analog Isolation Scheme 371 Figure 45 Noise Filter Scheme 371

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Tables

Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42:

VMEbus Address Modifier Codes 28 PCI Address Line Asserted as a Function of VA[15:11] 39 Command Type Encoding for Transfer Type 51 VMEbus Fields for VMEbus Slave Image. 67 PCI Bus Fields for VMEbus Slave Image 68 Control Fields for VMEbus Slave Image 68 PCI Bus Fields for the PCI Bus Target Image 70 VMEbus Fields for the PCI Bus Target Image 70 Control Fields for PCI Bus Target Image 71 PCI Bus Fields for the Special PCI Target Image 73 VMEbus Fields for the Special PCI Bus Target Image 73 Control Fields for the Special PCI Bus Target Image 73 Programming the VMEbus Register Access Image 79 VON Settings for Non-Inc Mode 88 DMA Interrupt Sources and Enable Bits 104 Source, Enabling, Mapping, and Status of PCI Interrupt Output. 112 Source, Enabling, Mapping, and Status of VMEbus Interrupt Outputs 114 Internal Interrupt Routing. 118 Hardware Reset Mechanisms 129 Software Reset Mechanism 130 Functions Affected by Reset Initiators. 132 Power-Up Options 135 VRAI Base Address Power-up Options 137 Manufacturing Pin Requirements for Normal Operating Mode 140 Test Mode Operation 141 VMEbus Signals. 144 PCI Bus Signals 147 Non-PCI Electrical Characteristics 153 AC/DC PCI Electrical Characteristics 154 Pin List and DC Characteristics for Universe II Signals 155 Operating Conditions 160 Absolute Maximum Ratings. 161 Power Dissipation 161 Universe II Register Map 164 Power-up Option Behavior of the VAS field in VRAI_CTL. 304 PCI Slave Channel Performance 352 VME Slave Channel Performance 352 DMA Channel Performance. 353 Ambient to Junction Thermal Impedance 357 Maximum Universe II Junction Temperature 357 Thermal Characteristics of Universe II 358 Mapping of 32-bit Little-Endian PCI Bus to 32-bit VMEbus 360

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Tables

Table 43 Table 44 Table 45 Table 46 Table 47:
Mapping of 32-bit Little-Endian PCI Bus to 64-bit VMEbus 361 VMEbus Signal Drive Strength Requirements 366 VMEbus Transceiver Requirements 366 Reset Signals 369 Standard Ordering Information 373

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About this Document

This section discusses the following topics
• “Scope” on page 13
• “Document Conventions” on page 13
• “Revision History” on page 15

Scope

The Universe IID/IIB User Manual discusses the features, capabilities, and configuration requirements for the Universe II. It is intended for hardware and software engineers who are designing system interconnect applications with the device.

Document Conventions

This document uses the following conventions.

Signal Notation

Signals are either active high or active low. Active low signals are defined as true asserted when they are at a logic low. Similarly, active high signals are defined as true at a logic high. Signals are considered asserted when active and negated when inactive, irrespective of voltage levels. For voltage levels, the use of 0 indicates a low voltage while a 1 indicates a high voltage.

For voltage levels, the use of 0 indicates a low voltage while a 1 indicates a high voltage. For voltage levels, the use of 0 indicates a low voltage while a 1 indicates a high voltage.

Each signal that assumes a logic low state when asserted is followed by an underscore sign, For example, SIGNAL_ is asserted low to indicate an active low signal. Signals that are not followed by an underscore are asserted when they assume the logic high state. For example, SIGNAL is asserted high to indicate an active high signal.

The asterisk sign “*” is used in this manual to show that a signal is asserted low and that is used on the on the VMEbus backplane. For example, SIGNAL* is asserted to low to indicate an active low signal on the VMEbus backplane.

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About this Document

Object Size Notation
• A byte is an 8-bit object.
• A word is a 16-bit object.
• A doubleword Dword is a 32-bit object.
• A quadword is a 64-bit 8 byte object.
• A Kword is 1024 16-bit words.

Numeric Notation
• Hexadecimal numbers are denoted by the prefix 0x for example, 0x04 .
• Binary numbers are denoted by the prefix 0b for example, 0b010 .
• Registers that have multiple iterations are denoted by in their names where x is first register
and address, and y is the last register and address. For example, indicates there are two versions of the register at different addresses REG0 and REG1.

Symbols

This symbol indicates a basic design concept or information considered helpful.

This symbol indicates important configuration information or suggestions.

This symbol indicates procedures or operating levels that may result in misuse or damage to the device.

Document Status Information
• Advance Contains information that is subject to change, and is available once prototypes are released to customers.
• Formal Contains information about a final, customer-ready product, and is available once the product is released to production.

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About this Document

May 12, 2010, Formal

This document fixed a number of minor typographical errors. No technical changes were made.

October 2009, Formal

This document was rebranded as IDT. No technical changes were made.

June 2009, Formal

There have been changes throughout the manual.

August 2007, Formal

There have been numerous edits throughout the manual. The formatting of the document has also been updated.

November 2002, Formal
Only aligned VMEbus transactions are generated, so if the requested PCI data beat has unaligned, or non-, byte enables, then it is broken into multiple aligned VMEbus transactions no wider than the programmed VMEbus data width. For example, consider a three-byte PCI data beat on a 32-bit PCI bus accessing a PCI target image with VDW set to 16 bits. The three-byte PCI data beat is broken into three aligned VMEbus cycles three single-byte cycle the ordering of the cycles depends on the arrangement of the byte enables in the PCI data beat . If in the above example the PCI target image has a VDW set to 8-bit, then the three-byte PCI data beat is broken into three single-byte VMEbus cycles.

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VMEbus Interface > Universe II as VMEbus Master

BLT/MBLT cycles are initiated on the VMEbus if the PCI target image has been programmed with this capacity see “PCI Bus Target Images” on page The length of the BLT/MBLT transactions on the VMEbus is determined by the initiating PCI transaction. For example, a single data beat PCI transaction queued in the TXFIFO results in a single data beat block transfer on the VMEbus. With the PWON field, the user can specify a transfer byte count that is queued from the TXFIFO before the VMEbus Master Interface relinquishes the VMEbus. The PWON field specifies the minimum tenure of the Universe II on the VMEbus. However, tenure is extended if the VOWN bit in the MAST_CTL register is set see “Using the VOWN bit” on page

During DMA operations, the Universe II attempts block transfers to the maximum length permitted by the VMEbus specification 256 bytes for BLT, 2 Kbytes for MBLT and is limited by the VON counter see “DMA VMEbus Ownership” on page

The Universe II provides indivisible transactions with the VMEbus lock commands and the VMEbus ownership bit see “VME Lock Access to VMEbus Resources” on page

Cycle Terminations

The Universe II accepts BERR* or DTACK* as cycle terminations from the VMEbus slave. It does not support RETRY*. The assertion of BERR* indicates that some type of system error occurred and the transaction did not complete properly. The assertion of BERR* during an IACK also causes the error to be logged.

A VMEbus BERR* received by the Universe II during a coupled transaction is communicated to the PCI master as a Target-Abort. No information is logged if the Universe II receives BERR* in a coupled transaction. If an error occurs during a posted write to the VMEbus or during an IACK cycle, the Universe II uses the “VMEbus AM Code Error Log V_AMERR ” on page 307 to log the AM code of the transaction AMERR [5:0] , and the state of the IACK* signal IACK bit, to indicate whether the error occurred during an IACK cycle . The current transaction in the FIFO is purged. The V_AMERR register also records if multiple errors have occurred with the M_ERR bit , although the actual number of errors is not given. The error log is qualified by the value of the V_STAT bit. The address of the errored transaction is latched in the “VMEbus Address Error Log VAERR ” on page When the Universe II receives a VMEbus error during a posted write, it generates an interrupt on the VMEbus and/or PCI bus depending upon whether the VERR and LERR interrupts are enabled see “Interrupt Handling” on page

DTACK* signals the successful completion of the transaction.

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VMEbus Interface > Universe II as VMEbus Slave

Universe II as VMEbus Slave

This section describes the VMEbus Slave Channel and other aspects of the Universe II as VMEbus slave.

The Universe II becomes VMEbus slave when one of its eight programmed slave images or register images are accessed by a VMEbus master. Depending upon the programming of the slave image, different possible transaction types can result see “VME Slave Image Programming” on page

The Universe II cannot reflect a cycle on the VMEbus and access itself.

For reads, the transaction can be coupled or prefetched. Write transactions can be coupled or posted. The type of read or write transaction allowed by the slave image depends on the programming of that particular VMEbus slave image see Figure 4 and “VME Slave Image Programming” on page To ensure sequential consistency, prefetched reads, coupled reads, and coupled write operations are only processed once all previously posted write operations have completed the RXFIFO is empty .

Figure 4 VMEbus Slave Channel Dataflow

PCI BUS MASTER INTERFACE

COUPLED WRITE DATA

RDFIFO

PREFETCHED READ DATA COUPLED READ DATA

VMEbus SLAVE INTERFACE

POSTED WRITE DATA

RXFIFO

Incoming cycles from the VMEbus can have data widths of 8-bit, 16-bit, 32-bit, and 64-bit. Although the PCI bus supports only two port sizes 32-bit and 64-bit , the byte lanes on the PCI bus can be individually enabled, which allows each type of VMEbus transaction to be directly mapped to the PCI data bus.

In order for a VMEbus slave image to respond to an incoming cycle, the PCI Master Interface must be enabled by setting the bit BM in the “PCI Configuration Space Control and Status Register PCI_CSR ” on page If data is queued in the VMEbus Slave Channel FIFO and the BM bit is cleared, the FIFO empties but no additional transfers are received.

Coupled Transfers

A coupled transfer means that no FIFO is involved in the transaction and handshakes are relayed directly through the Universe II. Coupled mode is the default setting for the VMEbus slave images.

Coupled transfers only proceed once all posted write entries in the RXFIFO have completed see “Posted Writes” on page

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VMEbus Interface > Universe II as VMEbus Slave

A coupled cycle with multiple data beats such as block transfers on the VMEbus side is always mapped to single data beat transactions on the PCI bus, where each data beat on the VMEbus is mapped to a single data beat transaction on the PCI bus regardless of data beat size. No packing or unpacking is performed. The only exception to this is when a D64 VMEbus transaction is mapped to D32 on the PCI bus. The data width of the PCI bus depends on the programming of the VMEbus slave image 32-bit or 64-bit, see “VME Slave Image Programming” on page The Universe II enables the appropriate byte lanes on the PCI bus as required by the VMEbus transaction. For example, a VMEbus slave image programmed to generate 32-bit transactions on the PCI bus is accessed by a VMEbus D08 BLT read transaction prefetching is not enabled in this slave image . The transaction is mapped to single data beat 32-bit transfers on the PCI bus with only one byte lane enabled.

Target-Retry from a PCI target is not communicated to the VMEbus master. PCI transactions terminated with Target-Abort or Master-Abort are terminated on the VMEbus with BERR*. The Universe II sets the R_TA or R_MA bits in the “PCI Configuration Space Control and Status Register PCI_CSR ” on page 172 when it receives a Target-Abort or Master-Abort.

Posted Writes

A posted write involves the VMEbus master writing data into the Universe II’s RXFIFO, instead of directly to the PCI address. Write transactions from the VMEbus are processed as posted if the PWEN bit is set in the VMEbus slave image control register see “VME Slave Image Programming” on page If the bit is cleared default setting the transaction bypasses the FIFO and is performed as a coupled transfer. Incoming posted writes from the VMEbus are queued in the 64-entry deep RXFIFO. Each entry in the RXFIFO can contain 32 address bits, or 64 data bits. Each incoming VMEbus address phase, whether it is 16-bit, 24-bit, or 32-bit, constitutes a single entry in the RXFIFO and is followed by subsequent data entries. The address entry contains the translated PCI address space and command information mapping relevant to the particular VMEbus slave image that has been accessed see “VME Slave Image Programming” on page For this reason, any reprogramming of VMEbus slave image attributes are only reflected in RXFIFO entries queued after the reprogramming. Transactions queued before the re-programming are delivered to the PCI bus with the VMEbus slave image attributes that were in use before the reprogramming.

The RXFIFO is the same structure as the RDFIFO. The different names are used for the FIFO’s two roles. In each FIFO, only one role, either the RXFIFO or the RDFIFO, can used at one time.

FIFO Entries
The PCI Bus Interface of the Universe II operates as a PCI compliant port with a 64-bit multiplexed address/data bus. The Universe II PCI Bus Interface is configured as little-endian using address invariant translation when mapping between the VMEbus and the PCI bus. Address invariant translation preserves the byte ordering of a data structure in a little-endian memory map and a big-endian memory map see “Endian Mapping” on page 359 and the PCI Specification .

The Universe II has all the PCI signals described in the PCI Specification with the exception of SBO_ and SDONE. These pins are exception because the Universe II does not provide cache support.

Universe II PCI cycles are synchronous, meaning that bus and control input signals are externally synchronized to the PCI clock CLK . PCI cycles are divided into the following phases Request Address Data transfer Cycle termination
32-Bit Versus 64-Bit PCI

The Universe II is configured with a 32-bit or 64-bit PCI data bus at power-up see “PCI Bus Width” on page

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PCI Interface > PCI Cycles

Each of the Universe II’s VMEbus slave images can be programmed so that VMEbus transactions are mapped to a 64-bit data bus on the PCI Interface through the LD64EN bit, in the “DMA Transfer Control Register DCTL ” on page If the VMEbus slave image is programmed with a 64-bit PCI bus data width and Universe II is powered-up in a 64-bit PCI environment, the Universe II asserts REQ64_ during the address phase of the PCI transaction.

REQ64_ is asserted if LD64EN is set in a 64-bit PCI system independent of whether the Universe II has a full 64-bit transfer. This can result in a performance degradation because of the extra clocks required to assert REQ64_ and to sample ACK64_. Also, there can be some performance degradation when accessing 32-bit targets with LD64EN set. Do not set the LD64EN bit unless there are 64-bit targets in the slave image window.

If the VMEbus slave images are not programmed for a 64-bit wide PCI data bus, then the Universe operates transparently in a 32-bit PCI environment.

Independent of the setting of the LD64EN bit, the Universe II never attempts a 64-bit cycle on the PCI bus if it is powered-up as a 32-bit device.

PCI Bus Request and Parking

The Universe II supports bus parking. If the Universe II requires the PCI bus it asserts REQ_ only if its GNT_ is not currently asserted. When the PCI Master Module is ready to begin a transaction and its GNT_ is asserted, the transfer begins immediately. This eliminates a possible one clock cycle delay before beginning a transaction on the PCI bus which would exist if the Universe II did not implement bus parking.

Refer to the PCI Specification for more information

Address Phase

PCI transactions are initiated by asserting FRAME_ and driving address and command information onto the bus. In the VMEbus Slave Channel, the Universe II calculates the address for the PCI transaction by adding a translation offset to the VMEbus address see “Universe II as VMEbus Slave” on page

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PCI Interface > PCI Cycles

The command signals on the C/BE_ lines contain information about Memory space, cycle type and whether the transaction is read or write. Table 3 shows the PCI command type encoding implemented with the Universe II.

Table 3 Command Type Encoding for Transfer Type

C/BE_ [3:0] for PCI, C/BE_ [7:4] for non-multiplexed 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100
1101 1110
1111

Command Type Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Memory Read Memory Write Reserved Configuration Read Configuration Write Memory Read Multiple

Dual Address Cycle Memory Read Line

Memory Write and Invalidate

Universe II Capability

N/A N/A Target/Master Target/Master N/A N/A Target/Master Target/Master N/A N/A Target/Master Target/Master See “Memory Read Types” on page 51 N/A See “Memory Read Types” on page 51 See “Memory Read Types” on page 51

Memory Read Types

Memory Read Multiple and Memory Read Line transactions are aliased to Memory Read transactions when the Universe II is accessed as a PCI target with these commands. Likewise, Memory Write and Invalidate is aliased to Memory Write. As a PCI master, the Universe II can generate Memory Read Multiple but not Memory Read Line.

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PCI Interface > PCI Cycles

PCI targets must assert DEVSEL_ if they have decoded the access. During a Configuration cycle, the target is selected by its particular ID Select IDSEL . If a target does not respond with DEVSEL_ within six clocks, a Master-abort is generated. The role of configuration cycles is described in the PCI Specification.

Data Transfer

Acknowledgment of a data phase occurs on the first rising clock edge after both IRDY_ and TRDY_ are asserted by the master and target, respectively. REQ64_ can be driven during the address phase to indicate that the master wishes to initiate a 64-bit transaction. The PCI target asserts ACK64_ if it is able to respond to the 64-bit transaction.

Wait cycles are introduced by either the master or the target by de-asserting IRDY_ or TRDY_. For write cycles, data is valid on the first rising edge after IRDY_ is asserted. Data is acknowledged by the target on the first rising edge with TRDY_ asserted. For read cycles, data is transferred and acknowledged on first rising edge with both IRDY_ and TRDY_ asserted.

A single data transfer cycle is repeated every time IRDY_ and TRDY_ are both asserted. The transaction only enters the termination phase when FRAME_ is de-asserted master-initiated termination or if STOP_ is asserted target-initiated . When both FRAME_ and IRDY_ are de-asserted final data phase is complete , the bus is defined as idle.

Termination Phase
The Universe II does not apply PCI Specification transaction ordering requirements to the DMA Controller. Reads and writes through the DMA Controller can occur independently of the other channels.

ADOH cycles and RMW cycles through the VMEbus Slave Channel do impact on the DMA Channel. Once an external VMEbus master locks the PCI bus, the DMA Controller does not perform transfers on the PCI bus until the Universe II is unlocked see “VMEbus Lock Commands ADOH Cycles ” on page When an external VMEbus Master begins a RMW cycle, at some point a read cycle appears on the PCI bus. During the time between when the read cycle occurs on the PCI bus and when the associated write cycle occurs on the PCI bus, no DMA transfers occurs on the PCI bus see “VMEbus Read-Modify-Write Cycles RMW Cycles ” on page

If the PCI Target Channel locks the VMEbus using VOWN, no DMA transfers takes place on the VMEbus see “Using the VOWN bit” on page

DMA Error Handling

This section describes how the Universe II responds to errors involving the DMA, and how the user can recover from them. The software source of a DMA error is a protocol, and the hardware source of a DMA error is a VMEbus error, or PCI bus Target-Abort or Master-Abort.

DMA Software Response to Error

While the DMA is operating normally, the ACT bit in the “DMA General Control/Status Register DGCS ” on page Once the DMA has terminated, it clears this bit, and sets one of six status bits in the same register. The DONE bit will be set if the DMA completed all its programmed operations normally. If the DMA is interrupted, either the STOP or HALT bits are set. If an error has occurred, one of the remaining three bits, LERR, VERR, or P_ERR, is set. All six forms of DMA terminations can be optionally set to generate a DMA interrupt by setting the appropriate enable bit in the DGCS register see “DMA Interrupts” on page
• LERR is set if the DMA encounters an error on the PCI bus either a Master-Abort or Target-Abort

Bits in the “PCI Configuration Space Control and Status Register PCI_CSR ” on page 172 indicate which of these conditions caused the error.

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DMA Controller > DMA Error Handling
• VERR is set if the DMA encounters a bus error on the VMEbus. This is through a detected assertion of BERR* during a DMA cycle.
• P_ERR is set if the GO bit in the DGCS register is set to start the DMA, and the DMA has been improperly programmed either because the BM bit in the PCI_CSR disables PCI bus mastership, or the source and destination start addresses are not aligned see “Source and Destination Addresses” on page

Whether the error occurs on the destination or source bus, the DMA_CTL register contains the attributes relevant to the particular DMA transaction. The DTBC register provides the number of bytes remaining to transfer on the PCI side. The DTBC register contains valid values after an error. The DLA and DVA registers should not be used for error recovery.

DMA Hardware Response to Error

When the error condition VMEbus Error, Target-Abort, or Master-Abort occurs on the source bus while the DMA is reading from the source bus, the DMA stops reading from the source bus. Any data previously queued within the DMAFIFO is written to the destination bus. Once the DMAFIFO empties, the error status bit is set and the DMA generates an interrupt if enabled by INT_LERR or INT_VERR in the DGCS “DMA Interrupts” on page

When the error condition VMEbus Error, Target-Abort, or Master-Abort occurs on the destination bus while the DMA is writing data to the destination bus, the DMA stops writing to the destination bus, and it also stops reading from the source bus. The error bit in the DGCS register is set and an interrupt asserted if enabled .

Interrupt Generation During Bus Errors

To generate an interrupt from a DMA error, there are two bits in the DGCS register, and one bit each in the VINT_EN and LINT_EN registers. In the DGCS register the INT_LERR bit enables the DMA to generate an interrupt to the Interrupt Channel after encountering an error on the PCI bus. The INT_VERR enables the DMA to generate an interrupt to the Interrupt Channel upon encountering an error on the VMEbus. Upon reaching the Interrupt Channel, all DMA interrupts can be routed to either the PCI bus or VMEbus by setting the appropriate bit in the enable registers. All DMA sources of interrupts Done, Stopped, Halted, VMEbus Error, and PCI Error constitute a single interrupt into the Interrupt Channel.

Resuming DMA Transfers

When a DMA error occurs on the source or destination bus , the status bits must be read in order to determine the source of the error. If it is possible to resume the transfer, the transfer should be resumed at the address that was in place up to 256 bytes from the current byte count. The original addresses DLA and DVA are required in order to resume the transfer at the appropriate location. However, the values in the DLA and the DVA registers should not be used to reprogram the DMA, because they are not valid once the DMA begins. In direct mode, it is the user’s responsibility to record the original state of the DVA and DLA registers for error recovery. In Linked-List mode, the user can refer to the current Command Packet stored on the PCI bus whose location is specified by the DCPP register for the location of the DVA and DLA information.

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DMA Controller > DMA Error Handling

The DTBC register contains the number of bytes remaining to transfer on the source side. The Universe II does not store a count of bytes to transfer on the destination side. If the error occurred on the source side, then the location of the error is simply the latest source address plus the byte count. If the error occurred on the destination side, then one cannot infer specifically where the error occurred, because the byte count only refers to the number of data queued from the source, not what has been written to the destination. In this case, the error will have occurred up to 256 bytes before the original address plus the byte count.

Given this background, the following procedure can be implemented to recover from errors.

Read the value contained in the DTBC register.

Read the record of the DVA and DLA that is stored on the PCI bus or elsewhere not the value stored in the Universe II registers of the same name .

If the difference between the value contained in the DTBC register and the original value is less than 512 bytes the FIFO depth of the Universe II , reprogram all the DMA registers with their original values.

If the difference between the value contained in the DTBC register and the original value is greater than 512 bytes the FIFO depth of the Universe II , add 512 bytes to the value contained in the DTBC register.

Add the difference between the original value in the DTBC and the new value in the DTBC register to the original value in the DLA register.

Add the difference between the original value in the DTBC and the new value in the DTBC register to the original value in the DVA register.

Clear the status flags.

Restart the DMA see “DMA Initiation” on page

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DMA Controller > DMA Error Handling

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Interrupt Generation and Handling
Universe II registers have little-endian byte-ordering.

Figure 24 below summarizes the supported register access mechanisms.

Figure 24 UCSR Access Mechanisms

VMEbus Configuration and Status Registers

VCSR

UNIVERSE DEVICE SPECIFIC REGISTERS

UDSR
4 Kbytes UCSR Space

PCI CONFIGURATION SPACE PCICS

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Registers > Register Map

Bits listed as reserved must be programmed with a value of Reserved bits always read a value of zero.

Register Map

Table 34 lists the Universe II registers by address offset.

Table 34 Universe II Register Map

Offset 0x000 0x004
0x008 0x00C 0x010 0x014 0x018-0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040-0x0FF 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C

Register “PCI Configuration Space ID Register PCI_ID ” on page 171 “PCI Configuration Space Control and Status Register PCI_CSR ” on page 172 “PCI Configuration Class Register PCI_CLASS ” on page 176 “PCI Configuration Miscellaneous 0 Register PCI_MISC0 ” on page 177 “PCI Configuration Base Address Register PCI_BS0 ” on page 178 “PCI Configuration Base Address 1 Register PCI_BS1 ” on page 179 PCI Unimplemented PCI Reserved PCI Reserved PCI Unimplemented PCI Reserved PCI Reserved “PCI Configuration Miscellaneous 1 Register PCI_MISC1 ” on page 180 PCI Unimplemented “PCI Target Image 0 Control LSI0_CTL ” on page 181 “PCI Target Image 0 Base Address Register LSI0_BS ” on page 183 “PCI Target Image 0 Bound Address Register LSI0_BD ” on page 184 “PCI Target Image 0 Translation Offset LSI0_TO ” on page 185 Reserved “PCI Target Image 1 Control LSI1_CTL ” on page 186 “PCI Target Image 1 Base Address Register LSI1_BS ” on page 188 “PCI Target Image 1 Bound Address Register LSI1_BD ” on page 189

Name PCI_ID PCI_CSR PCI_CLASS PCI_MISC0 PCI_BS0 PCI_BS1

PCI_MISC1

LSI0_CTL LSI0_BS LSI0_BD LSI0_TO

LSI1_CTL LSI1_BS LSI1_BD

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Registers > Register Map

Table 34 Universe II Register Map Continued

Offset 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C 0x140 0x144 0x148 0x14C-0x16C 0x170 0x174 0x178
0x17C 0x180 0x184 0x188 0x18C 0x190 0x194-0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0

Register “PCI Target Image 1 Translation Offset LSI1_TO ” on page 190 Reserved “PCI Target Image 2 Control LSI2_CTL ” on page 191 “PCI Target Image 2 Base Address Register LSI2_BS ” on page 193 “PCI Target Image 2 Bound Address Register LSI2_BD ” on page 194 “PCI Target Image 2 Translation Offset LSI2_TO ” on page 195 Reserved “PCI Target Image 3 Control LSI3_CTL ” on page 196 “PCI Target Image 3 Base Address Register LSI3_BS ” on page 198 “PCI Target Image 3 Bound Address Register LSI3_BD ” on page 199 “PCI Target Image 3 Translation Offset LSI3_TO ” on page 200 Reserved “Special Cycle Control Register SCYC_CTL ” on page 201 “Special Cycle PCI Bus Address Register SCYC_ADDR ” on page 202 “Special Cycle Swap/Compare Enable Register SCYC_EN ” on page 203 “Special Cycle Compare Data Register SCYC_CMP ” on page 204 “Special Cycle Swap Data Register SCYC_SWP ” on page 205 “PCI Miscellaneous Register LMISC ” on page 206 “Special PCI Target Image SLSI ” on page 208 “PCI Command Error Log Register L_CMDERR ” on page 210 “PCI Address Error Log LAERR ” on page 211 Reserved “PCI Target Image 4 Control Register LSI4_CTL ” on page 212 “PCI Target Image 4 Base Address Register LSI4_BS ” on page 214 “PCI Target Image 4 Bound Address Register LSI4_BD ” on page 215 “PCI Target Image 4 Translation Offset LSI4_TO ” on page 216 Reserved

Name LSI1_TO

LSI2_CTL LSI2_BS LSI2_BD LSI2_TO

LSI3_CTL LSI3_BS LSI3_BD LSI3_TO

SCYC_CTL SCYC_ADDR

SCYC_EN

SCYC_CMP SCYC_SWP

LMISC SLSI L_CMDERR LAERR

LSI4_CTL LSI4_BS LSI4_BD LSI4_TO

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Registers > Register Map
The Universe II always performs Address Invariant translation between the PCI and VMEbus ports. Address Invariant mapping preserves the byte ordering of a data structure in a little-endian memory map and a big-endian memory map.

Little-endian Mode

Table 42 shows the byte lane swapping and address translation between a 32-bit little-endian PCI bus and the VMEbus for the address invariant translation scheme.

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D. Endian Mapping > Little-endian Mode

Table 42 Mapping of 32-bit Little-Endian PCI Bus to 32-bit VMEbus

PCI Bus

Byte Enables

Address

VMEbus

Byte Lane Mapping

DS1 DS0 A1 LW

D0-D7

D8-D15

D8-D15

D0-D7

D16-D23

D8-D15

D24-D31

D0-D7

D0-D7

D8-D15

D8-D15

D0-D7

D8-D15

D16-D23

D16-D23

D8-D15

D16-D23

D8-D15

D24-D31

D0-D7

D0-D7

D24-D31

D8-D15

D16-D23

D16-D23

D8-D15

D8-D15

D16-D23
F. Ordering Information
This appendix discusses Universe II’s ordering information.
Ordering Information
IDT products are designated by a product code. When ordering, refer to products by their full code. Table 47 details the available part numbers.
Table 47 Standard Ordering Information

Part Number CA91C142D-33CE CA91C142D-33CEV

PCI Frequency 33 MHz 33 MHz

CA91C142D-33IE CA91C142D-33IEV
33 MHz 33 MHz

CA91C142D-25EE
25 MHz

Voltage 5V

Temperature

Package

Commercial 0° to 70°C

PBGA

Commercial 0° to 70°C

PBGA RoHS/Green

Industrial -40° to 85°C

PBGA

Industrial

PBGA
-40° to 85°C RoHS/Green

Extended -55° to 125°C

PBGA

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F. Ordering Information > Ordering Information

The IDT “Tsi” part numbering system is explained as follows. Tsi NNN N - SS S E P G Z#

IDT product identifier Product number

Operating frequency Operating environment

Package type RoHS/Green compliance

Prototype version status
• Indicates optional characters.
• Tsi IDT “Tsi” product identifier.
• NNNN Product number may be three or four digits .
• SS S Maximum operating frequency or data transfer rate of the fastest interface. For operating
frequency numbers, M and G represent MHz and GHz. For transfer rate numbers, M and G represent Mbps and Gbps.
• E Operating environment in which the product is guaranteed. This code may be one of the following characters C - Commercial temperature range 0 to +70°C I - Industrial temperature range -40 to +85°C E - Extended temperature range -55 to +125°C
• P The Package type of the product B - Ceramic ball grid array CBGA E, L, J, and K - Plastic ball grid array PBGA G - Ceramic pin grid array CPGA M - Small outline integrated circuit SOIC Q - Plastic quad flatpack QFP

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F. Ordering Information > Ordering Information
• G IDT “Tsi” products fit into three RoHS-compliance categories:

Y - RoHS Compliant 6of6 These products contain none of the six restricted substances above the limits set in the EU Directive 2002/95/EC.

Y - RoHS Compliant Flip Chip These products contain only one of the six restricted substances Lead Pb . These flip-chip products are RoHS compliant through the Lead exemption for Flip Chip technology, Commission Decision 2005/747/EC, which allows Lead in solders to complete a viable electrical connection between semiconductor die and carrier within integrated circuit Flip Chip packages.

V - RoHS Compliant/Green - These products follow the above definitions for RoHS Compliance and meet JIG Joint Industry Guide Level B requirements for Brominated Flame Retardants other than PBBs and PBDEs .

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F. Ordering Information > Ordering Information

Universe II User Manual May 12, 2010

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May 2010

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CA91C142D-33IE Datasheet file may be downloaded here without warranties.

Datasheet ID: CA91C142D-33IE 637528