IDT79RC32T365-150BC

IDT79RC32T365-150BC Datasheet

IDTTM InterpriseTM Integrated Communications Processor

Part	Datasheet
IDT79RC32T365-150BC	IDT79RC32T365-150BC (pdf)

Related Parts	Information
IDT79RC32T365-150BCG	IDT79RC32T365-150BCG

PDF Datasheet Preview
IDTTM InterpriseTM Integrated Communications Processor RC32365 Device Overview The RC32365 device is a member of the IDT Interprise family of integrated communications processors. This device is designed to address a range of communications applications that require the efficient processing of IPSec algorithms. These applications include gateways, wireless access points, and virtual private network VPN equipment. The key to the RC32365’s efficient processing of IPSec algorithms is a highly progammable security engine which off-loads the CPU core of encryption/decryption, hashing, and padding tasks. Features List RC32300 32-bit CPU core 32-bit MIPS instruction set Supports big or little endian operation MMU 16-entry TLB Supports variable page sizes and enhanced write algorithm Supports variable number of locked entries 8KB Instruction Cache 2-way set associative LRU replacement algorithm 4 word line size Sub-block ordering Word parity Per line cache locking 2KB Data Cache 2-way set associative LRU replacement algorithm 4 word line size Sub-block ordering Byte parity Per line cache locking Can be programmed on a page basis to implement write- through no write allocate, write-through write allocate, or write-back algorithms Enhanced EJTAG and JTAG Interfaces Compatible with IEEE Std. Security Engine Dedicated DMA channels for high speed data transfers to and from the security engine On-chip memory for storage of two security contexts Supports ECB and CBC modes for the following symmetric encryption algorithms DES, triple DES both two key k1=k3 and three key k1!=k3 modes , AES-128 with 128-bit blocks, AES-192 with 128-bit blocks Hardware support for encryption pad generation and checking using one of seven popular padding algorithms supports pad algorithm required by IPSec ESP Supports MD5 and SHA-1 one-way hash functions Programmable truncation length of computed hash and HMAC on a security context basis Supports concurrent hash and encryption operations Block Diagram JTAG 32-bit MIPS CPU Core EJTAG D. Cache I. Cache Interrupt Controller 2 Ethernet Bus/System 10/100 Integrity Interfaces Monitor Security Functions Security Context Storage Hash Unit Encryption Unit DMA Controller IPBusTM Arbiter SDRAM & Device Controllers including PCMCIA Support 3 Counter Timers UART 16550 GPIO Interface Controller Master/Target Interface PCI Arbiter Host Mode Memory & Peripheral Bus including PCMCIA Serial Channel GPIO Pins SPI Bus PCI Bus Figure 1 RC32365 Internal Block Diagram 2005 Integrated Device Technology, Inc. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. 1 of 44 Ordering Information 79RCXX Product Type Operating Voltage XXXX Device Type 999 Speed A Package Temp range/ Process Blank I BC BCG 150 Commercial Temperature 0°C to +70°C Ambient Industrial Temperature -40° C to +85° C Ambient 256-pin CABGA 256-pin Green CABGA 150 MHz Pipeline Clk Integrated Core Processor 2.5V +/-5% Core Voltage 32-bit Embedded 79RC32 Microprocessor Valid Combinations 79RC32T365 - 150BC 79RC32T365 - 150BCG 79RC32T365 - 150BCI 79RC32T365 - 150BCGI 256-pin CABGA package, Commercial Temperature 256-pin CABGA package, Commercial Temperature Green 256-pin CABGA package, Industrial Temperature 256-pin CABGA package, Industrial Temperature Green CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 44 of 44 for Tech Support email phone 408-284-8208 October 5, 2005

PDF Datasheet Preview

IDTTM InterpriseTM Integrated Communications Processor

RC32365

Device Overview

The RC32365 device is a member of the IDT Interprise family of integrated communications processors. This device is designed to address a range of communications applications that require the efficient processing of IPSec algorithms. These applications include gateways, wireless access points, and virtual private network VPN equipment. The key to the RC32365’s efficient processing of IPSec algorithms is a highly progammable security engine which off-loads the CPU core of encryption/decryption, hashing, and padding tasks.

Features List
RC32300 32-bit CPU core 32-bit MIPS instruction set Supports big or little endian operation MMU 16-entry TLB Supports variable page sizes and enhanced write algorithm Supports variable number of locked entries 8KB Instruction Cache 2-way set associative LRU replacement algorithm 4 word line size Sub-block ordering Word parity Per line cache locking 2KB Data Cache
2-way set associative LRU replacement algorithm 4 word line size Sub-block ordering Byte parity Per line cache locking Can be programmed on a page basis to implement write-
through no write allocate, write-through write allocate, or write-back algorithms Enhanced EJTAG and JTAG Interfaces Compatible with IEEE Std.

Security Engine

Dedicated DMA channels for high speed data transfers to and from the security engine

On-chip memory for storage of two security contexts Supports ECB and CBC modes for the following symmetric
encryption algorithms DES, triple DES both two key k1=k3 and three key k1!=k3 modes , AES-128 with 128-bit blocks, AES-192 with 128-bit blocks Hardware support for encryption pad generation and checking using one of seven popular padding algorithms supports pad algorithm required by IPSec ESP Supports MD5 and SHA-1 one-way hash functions Programmable truncation length of computed hash and HMAC on a security context basis Supports concurrent hash and encryption operations

Block Diagram

JTAG
32-bit MIPS CPU Core

EJTAG

D. Cache I. Cache

Interrupt

Controller
2 Ethernet

Bus/System 10/100 Integrity Interfaces

Monitor

Security Functions

Security

Context Storage

Hash Unit

Encryption Unit

DMA Controller

IPBusTM

Arbiter

SDRAM & Device Controllers
including PCMCIA Support
3 Counter Timers

UART 16550

GPIO Interface

Controller

Master/Target Interface

PCI Arbiter Host Mode

Memory & Peripheral Bus
including PCMCIA

Serial Channel

GPIO Pins SPI Bus

PCI Bus

Figure 1 RC32365 Internal Block Diagram
2005 Integrated Device Technology, Inc.

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1 of 44
Ordering Information
79RCXX

Product Type

Operating Voltage

XXXX

Device Type
999 Speed

A Package

Temp range/ Process

Blank I

BC BCG 150

Commercial Temperature 0°C to +70°C Ambient Industrial Temperature -40° C to +85° C Ambient
256-pin CABGA 256-pin Green CABGA
150 MHz Pipeline Clk

Integrated Core Processor
2.5V +/-5% Core Voltage
32-bit Embedded 79RC32 Microprocessor

Valid Combinations
79RC32T365 - 150BC 79RC32T365 - 150BCG 79RC32T365 - 150BCI 79RC32T365 - 150BCGI
256-pin CABGA package, Commercial Temperature 256-pin CABGA package, Commercial Temperature Green 256-pin CABGA package, Industrial Temperature 256-pin CABGA package, Industrial Temperature Green

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
44 of 44
for Tech Support email phone 408-284-8208

October 5, 2005

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT79RC32T365-150BC Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT79RC32T365-150BC 637505