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IDTQS5917T-132TJ8 (pdf) |
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IDTQS5917T-132TQG8 |
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IDTQS5917T-132TQG |
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IDTQS5917T-100TQG8 |
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QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE QS5917T FEATURES: • 5V operation • 2xQ output, Q/2 output, Q output • Outputs tri-state while RST low • Internal loop filter RC network • Low noise TTL level outputs • < 500ps output skew, Q0-Q4 • PLL disable feature for low frequency testing • Balanced Drive Outputs ± 24mA • 132MHz maximum frequency 2xQ output • Functional equivalent to Motorola MC88915 • ESD > 2000V • Latch-up > • Available in QSOP and PLCC packages FUNCTIONAL BLOCK DIAGRAM The QS5917T Clock Driver uses an internal phase locked loop PLL to lock low skew outputs to one of two reference clock inputs. Eight outputs are available Q0-Q4, 2xQ, Q/2, Q5. Careful layout and design insures < 500ps skew between the Q0-Q4, and Q/2 outputs. The QS5917T includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. In addition, TTL level outputs reduce clock signal noise. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The VCO can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The LOCK output asserts to indicate when phase lock has been achieved. The QS5917T is designed for use in high-performance workstations, multi-board computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. For more information on PLL clock driver products, see Application Note AN-227. SYNC0 SYNC1 RST REF_SEL 0 1 LOCK FEEDBACK PHASE DETECTOR LOOP FILTER PLL_EN FREQ_SEL The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 2006 Integrated Device Technology, Inc. SEPTEMBER 2006 DSC-5227/4 QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER PIN CONFIGURATION INDUSTRIAL TEMPERATURE RANGE GND Q5 VDD RST FEEDBACK REF_SEL SYNC0 AVDD NC AGND SYNC1 FREQ_SEL GND Q0 QSOP TOP VIEW Q4 VDD 2xQ Q/2 GND Q3 VDD Q2 GND LOCK PLL_EN GND Q1 VDD RST VDD Q5 GND Q4 VDD 2xQ 4 3 2 1 28 27 26 FEEDBACK 5 25 Q/2 REF_SEL 6 24 GND SYNC0 7 23 Q3 AVDD 8 22 VDD 21 Q2 ORDERING INFORMATION QS XXXX Device Type Speed Package Process INDUSTRIAL TEMPERATURE RANGE Blank Industrial -40°C to +85°C Quarter Size Outline Package QG QSOP - Green Plastic Leaded Chip Carrier PLCC - Green -70T 70MHz Max. Frequency -100T 100MHz Max. Frequency -132T 132MHz Max. Frequency 5917T Low Skew CMOS PLL Clock Driver with Integrated Loop Filter CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support: |
More datasheets: MT18HTF12872PZ-667G1 | MT18HTF25672PZ-80EH1 | MT18HTF25672PZ-667H1 | VSC452XHW-05 | MIKROE-2336 | IDTQS5917T-100TQG | IDTQS5917T-70TQG8 | IDTQS5917T-70TQG | IDTQS5917T-132TQG8 | IDTQS5917T-132TQG |
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