MC88915EI55

MC88915EI55 Datasheet

MC88915

Part	Datasheet
MC88915EI55	MC88915EI55 (pdf)

Related Parts	Information
MC88915EI70R2	MC88915EI70R2
MC88915EI70	MC88915EI70
MC88915EI55R2	MC88915EI55R2
MC88915FN70	MC88915FN70
MC88LV915TEI	MC88LV915TEI
MC88LV915TEIR2	MC88LV915TEIR2
MC88915FN55R2	MC88915FN55R2

PDF Datasheet Preview
Low Skew CMOS PLL Clock Drivers MC88915 The MC88915 Clock Driver utilizes phase-locked loop technology to lock its low skew outputs' frequency and phase onto an input reference clock. It is designed to provide clock distribution for high performance PC's and workstations. The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it to multiple components on a board. The PLL also allows the MC88915 to multiply a low frequency input clock and distribute it locally at a higher 2X system frequency. Multiple 88915's can lock onto a single reference clock, which is ideal for applications when a central system clock must be distributed synchronously to multiple boards see Figure Five “Q” outputs QO-Q4 are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted 180° phase shift from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q” frequency. The VCO is designed to run optimally between 20 MHz and the 2X_Q Fmax specification. The wiring diagrams in Figure 5 detail the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the “Q” outputs to the SYNC input are 2:1, 1:1, and The FREQ_SEL pin provides one bit programmable divide-by in the feedback path of the PLL. It selects between divide-by-1 and divide-by-2 of the VCO before its signal reaches the internal clock distribution section of the chip see the block diagram on page In most applications FREQ_SEL should be held high If a low frequency reference clock input is used, holding FREQ_SEL low ÷2 will allow the VCO to run in its optimal range >20 MHz . In normal phase-locked operation, the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88915 in a static “test mode”. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board test environment. The second SYNC input can be used as a test clock input to further simplify board-level testing see detailed description on page A lock indicator output LOCK will go high when the loop is in steady-state phase and frequency lock. The LOCK output will go low if phase-lock is lost or when the PLL_EN pin is low. Under certain conditions the lock output may remain low, even though the part is phase-locked. Therefore, the LOCK output signal should not be used to drive any active circuitry it should be used for passive monitoring or evaluation purposes only. MC88915 LOW SKEW CMOS PLL CLOCK DRIVER FN SUFFIX 28-LEAD PLCC PACKAGE CASE 776-02 EI SUFFIX 28-LEAD PLCC PACKAGE Pb-FREE PACKAGE CASE 776-02 • Five outputs with output-output skew < 500 ps, each being phase and frequency locked to the SYNC input • The phase variation from part-to-part between the SYNC and FEEDBACK inputs is less than 550 ps derived from the tPD specification, defining the part-to-part skew . • Input/output phase-locked frequency ratios of 1:2, 1:1, and 2:1 are available • Input frequency range from 5 MHz 2X_Q fmax specification • Additional outputs available at 2X and +2 the system “Q” frequency. Also, a Q 180° phase shift output available • All outputs have ±36 mA drive equal high and low at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are TTL-level compatible. • Test mode pin PLL_EN provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes. • 28-lead Pb-free package available. IDT / ICS CMOS PLL CLOCK DRIVERS MC88915 LOW SKEW CMOS PLL CLOCK DRIVERS FEEDBACK REF_SEL SYNC[0] VCC AN RC1 GND AN SYNC[1] RST VCC Q5 GND Q4 VCC 2X_Q 4 3 2 1 28 27 26 12 13 14 15 16 17 18 Q/2 GND Q3 VCC Q2 GND LOCK FREQ_SEL GND Q0 VCC Q1 GND PLL_EN Figure Pinout 28-Lead PLCC Top View Table Pin Summary Pin Name SYNC[0] SYNC[1] REF_SEL FREQ_SEL FEEDBACK Q5 2x_Q Q/2 LOCK RST PLL_EN VCC, GND Number 1 5 1 11 I/O Input Output Input Function Reference clock input Reference clock input Chooses reference between SYNC[0] and SYNC[1] Selects Q output frequency Feedback input to phase detector Input for external RC network Clock output locked to SYNC Inverse of clock output 2 x clock output Q frequency synchronous Clock output Q frequency ÷ 2 synchronous Indicates phase lock has been achieved high when locked Asynchronous reset active low Disables phase-lock for low frequency testing Power and ground pins note pins 8 and 10 are “quiet” supply pins for internal logic only IDT / ICS CMOS PLL CLOCK DRIVERS MC88915 LOW SKEW CMOS PLL CLOCK DRIVERS FEEDBACK SYNC 0 SYNC 1 REF_SEL PHASE/FREQ DETECTOR LOCK CHARGE PUMP/LOOP FILTER VOLTAGE CONTROLLED OSCILLATOR

PDF Datasheet Preview

Low Skew CMOS PLL Clock Drivers

MC88915

The MC88915 Clock Driver utilizes phase-locked loop technology to lock its low skew outputs' frequency and phase onto an input reference clock. It is designed to provide clock distribution for high performance PC's and workstations.

The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it to multiple components on a board. The PLL also allows the MC88915 to multiply a low frequency input clock and distribute it locally at a higher 2X system frequency. Multiple 88915's can lock onto a single reference clock, which is ideal for applications when a central system clock must be distributed synchronously to multiple boards see Figure

Five “Q” outputs QO-Q4 are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted 180° phase shift from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q” frequency.

The VCO is designed to run optimally between 20 MHz and the 2X_Q Fmax specification. The wiring diagrams in Figure 5 detail the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the “Q” outputs to the SYNC input are 2:1, 1:1, and

The FREQ_SEL pin provides one bit programmable divide-by in the feedback path of the PLL. It selects between divide-by-1 and divide-by-2 of the VCO before its signal reaches the internal clock distribution section of the chip see the block diagram on page In most applications FREQ_SEL should be held high If a low frequency reference clock input is used, holding FREQ_SEL low ÷2 will allow the VCO to run in its optimal range >20 MHz .

In normal phase-locked operation, the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88915 in a static “test mode”. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board test environment. The second SYNC input can be used as a test clock input to further simplify board-level testing see detailed description on page

A lock indicator output LOCK will go high when the loop is in steady-state phase and frequency lock. The LOCK output will go low if phase-lock is lost or when the PLL_EN pin is low. Under certain conditions the lock output may remain low, even though the part is phase-locked. Therefore, the LOCK output signal should not be used to drive any active circuitry it should be used for passive monitoring or evaluation purposes only.

MC88915

LOW SKEW CMOS PLL CLOCK DRIVER

FN SUFFIX 28-LEAD PLCC PACKAGE

CASE 776-02

EI SUFFIX 28-LEAD PLCC PACKAGE

Pb-FREE PACKAGE CASE 776-02
• Five outputs with output-output skew < 500 ps, each being phase and frequency locked to the SYNC input
• The phase variation from part-to-part between the SYNC and FEEDBACK inputs is less than 550 ps derived from the tPD specification,
defining the part-to-part skew .
• Input/output phase-locked frequency ratios of 1:2, 1:1, and 2:1 are available
• Input frequency range from 5 MHz 2X_Q fmax specification
• Additional outputs available at 2X and +2 the system “Q” frequency. Also, a Q 180° phase shift output available
• All outputs have ±36 mA drive equal high and low at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are

TTL-level compatible.
• Test mode pin PLL_EN provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes.
• 28-lead Pb-free package available.

IDT / ICS CMOS PLL CLOCK DRIVERS

MC88915 LOW SKEW CMOS PLL CLOCK DRIVERS

FEEDBACK REF_SEL SYNC[0] VCC AN RC1 GND AN SYNC[1]

RST VCC Q5 GND Q4 VCC 2X_Q
4 3 2 1 28 27 26
12 13 14 15 16 17 18

Q/2 GND Q3 VCC Q2 GND LOCK

FREQ_SEL GND Q0 VCC Q1 GND PLL_EN

Figure Pinout 28-Lead PLCC Top View

Table Pin Summary

Pin Name SYNC[0] SYNC[1] REF_SEL FREQ_SEL FEEDBACK

Q5 2x_Q Q/2 LOCK RST PLL_EN VCC, GND

Number 1 5 1 11

I/O Input Output Input

Function Reference clock input Reference clock input Chooses reference between SYNC[0] and SYNC[1] Selects Q output frequency Feedback input to phase detector Input for external RC network Clock output locked to SYNC Inverse of clock output 2 x clock output Q frequency synchronous Clock output Q frequency ÷ 2 synchronous Indicates phase lock has been achieved high when locked Asynchronous reset active low Disables phase-lock for low frequency testing Power and ground pins note pins 8 and 10 are “quiet” supply pins for internal logic only

IDT / ICS CMOS PLL CLOCK DRIVERS

MC88915 LOW SKEW CMOS PLL CLOCK DRIVERS

FEEDBACK

SYNC 0 SYNC 1 REF_SEL

PHASE/FREQ DETECTOR

LOCK

CHARGE PUMP/LOOP FILTER

VOLTAGE CONTROLLED OSCILLATOR

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Datasheet ID: MC88915EI55 637429