MC100ES6222AE

MC100ES6222AE Datasheet

MC100ES6222

Part	Datasheet
MC100ES6222AE	MC100ES6222AE (pdf)

Related Parts	Information
MC100ES6222AER2	MC100ES6222AER2

PDF Datasheet Preview
LOW VOLTAGE, 1:15 DIFFERENTIAL ECL/PECL CLOCK DIVIDER AND FANOUT BUFFER MC100ES6222 The MC100ES6222 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6222 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems. LOW-VOLTAGE 1:15 DIFFERENTIAL ECL/PECL CLOCK DIVIDER AND FANOUT DRIVER • 15 differential ECL/PECL outputs 4 output banks • 2 selectable differential ECL/PECL inputs • Selectable ÷1 or ÷2 frequency divider • 130 ps maximum device skew • Supports DC to 3 GHz input frequency • Single V, V, V or V supply • Standard 52-lead LQFP package with exposed pad for enhanced thermal characteristics • Supports industrial temperature range • Pin and function compatible to the MC100EP222 • 52-lead Pb-free Package Available TB SUFFIX 52-LEAD LQFP PACKAGE EXPOSED PAD CASE 1336A-01 Functional Description The MC100ES6222 is designed for low skew clock distribution systems and supports AE SUFFIX clock frequencies up to 3 GHz. The CLK0 and CLK1 inputs can be driven by ECL or PECL 52-LEAD LQFP PACKAGE compatible signals. Each of the four output banks of two, three, four and six differential EXPOSED PAD clock output pairs can be independently configured to distribute the input frequency or ÷2 of the input frequency. The FSELA, FSELB, FSELC, FSELD, and CLK_SEL are Pb-FREE PACKAGE CASE 1336A-01 asychronous control inputs. Any changes of the control inputs require a MR pulse for resynchronization of the ÷2 outputs. For the functionality of the MR control input, see Figure Functional Diagram. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6222 can be operated from a single V or V supply. As most other ECL compatible devices, the MC100ES6222 supports positive PECL and negative ECL supplies. The MC100ES6222 is pin and function compatible to the MC100EP222. IDT / ICS ECL/PECL CLOCK DIVIDER AND FANOUT BUFFER MC100ES6222 LOW VOLTAGE, 1:15 DIFFERENTIAL, ECL/PECL CLOCK DIVIDER AND FANOUT BUFFER ADVANCED CLOCK DRIVERS FSELA VEE CLK0 CLK0 0 ÷1 1 ÷2 CLK1 VEE CLK_SEL VEE FSELB FSELC 0 VEE MR VEE FSELD QA0 QA1 QB1 VCC 4039 38 37 36 35 34 33 32 31 30 29 28 2726 QC0 QB1

PDF Datasheet Preview

LOW VOLTAGE, 1:15 DIFFERENTIAL ECL/PECL CLOCK DIVIDER AND FANOUT BUFFER

MC100ES6222

The MC100ES6222 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6222 supports various applications that require the distribution of precisely aligned differential clock signals. Using SiGe technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems.

LOW-VOLTAGE 1:15 DIFFERENTIAL ECL/PECL CLOCK DIVIDER AND FANOUT DRIVER
• 15 differential ECL/PECL outputs 4 output banks
• 2 selectable differential ECL/PECL inputs
• Selectable ÷1 or ÷2 frequency divider
• 130 ps maximum device skew
• Supports DC to 3 GHz input frequency
• Single V, V, V or V supply
• Standard 52-lead LQFP package with exposed pad for enhanced thermal
characteristics
• Supports industrial temperature range
• Pin and function compatible to the MC100EP222
• 52-lead Pb-free Package Available

TB SUFFIX 52-LEAD LQFP PACKAGE

EXPOSED PAD CASE 1336A-01

Functional Description

The MC100ES6222 is designed for low skew clock distribution systems and supports

AE SUFFIX
clock frequencies up to 3 GHz. The CLK0 and CLK1 inputs can be driven by ECL or PECL
52-LEAD LQFP PACKAGE
compatible signals. Each of the four output banks of two, three, four and six differential

EXPOSED PAD
clock output pairs can be independently configured to distribute the input frequency or ÷2 of the input frequency. The FSELA, FSELB, FSELC, FSELD, and CLK_SEL are

Pb-FREE PACKAGE CASE 1336A-01
asychronous control inputs. Any changes of the control inputs require a MR pulse for
resynchronization of the ÷2 outputs. For the functionality of the MR control input, see

Figure Functional Diagram.

In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only
one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on
that side should be terminated.

The MC100ES6222 can be operated from a single V or V supply. As most other ECL compatible devices, the MC100ES6222
supports positive PECL and negative ECL supplies. The MC100ES6222 is pin and function compatible to the MC100EP222.

IDT / ICS ECL/PECL CLOCK DIVIDER AND FANOUT BUFFER

MC100ES6222 LOW VOLTAGE, 1:15 DIFFERENTIAL, ECL/PECL CLOCK DIVIDER AND FANOUT BUFFER ADVANCED CLOCK DRIVERS

FSELA

VEE CLK0

CLK0
0 ÷1
1 ÷2

CLK1

VEE CLK_SEL

VEE FSELB FSELC
0 VEE MR

VEE FSELD

QA0 QA1

QB1 VCC
4039 38 37 36 35 34 33 32 31 30 29 28 2726

QC0 QB1

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MC100ES6222AE Datasheet file may be downloaded here without warranties.

Datasheet ID: MC100ES6222AE 637426