IDTCV183-2BPAG

IDTCV183-2BPAG Datasheet

IDTCV183-2B PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

Part	Datasheet
IDTCV183-2BPAG	IDTCV183-2BPAG (pdf)

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IDTCV183-2B PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR COMMERCIAL TEMPERATURE RANGE PROGRAMMABLE FLEXPC CLOCK IDTCV183-2B FEATURES: • Compliant with Intel CK505 Gen II spec • One high precision PLL for CPU, SSC and N programming • One high precision PLL for SRC, SSC and N programming • One high precision PLL for SATA/PCI, and SSC • One high precision PLL for 96MHz/48MHz • Push-pull IOs for differential outputs • Support spread spectrum modulation, down spread and others • Support SMBus block read/write, byte read/write • Available in TSSOP package KEY FEATURES • Internal serial resistor can be enabled by SMBus control register B19b7 to save the board space and material cost • Direct CPU and SRC clock frequency the Hex number into Byte [16:18], 1 MHz stepping. • Linear and smooth transition for the CPU and SRC frequency programming. • Four Power On hardware modes see page 6, CFG configuration table • CV183-2 When CFG[1:0] = 11, SATA clock power on default is from SRC PLL. OUTPUTS: • 20.7V differential CPU CLK pair • 100.7V differential SRC CLK pair • One CPU_ITP/SRC differential clock pair • One SRC0/DOT96 differential clock pair • 6PCI, 33.3MHz • 148MHz • 1REF • 1SATA KEY SPECIFICATIONS: • CPU/SRC CLK cycle to cycle jitter < 85ps • PCI CLK cycle to cycle jitter < 500ps • All SRC, SRC[0:11] phase noise < 3.10s RMS, PCIE Gen II • SRC3, 4, 6, 7, designated PCIE Gen II outputs, nominal interpair skew = 0 ps FUNCTIONAL BLOCK DIAGRAM XTAL_IN XTAL_OUT SDATA SCLK XTAL Osc Amp SM Bus Controller CKPWRGD/PD# CPU_STOP# PCI_STOP# SRC5_EN, TME ITP_EN CR_[H:A]# FSC,B,A Control Logic PLL1 SSC N Programmable PLL3 SSC PLL4 SSC N Programmable Fixed PLL PLL2 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 2011 Integrated Device Technology, Inc. CPU Output Buffer Stop Logic PCI/SATA SRC CLK Output Buffer Stop Logic SRC CLK Output Buffer Stop Logic 48MHz/96MHz Output BUffer REF CPU[1:0] CPU_ITP/SRC8 SRC1/SE PCI[4:0], PCIF5 SATA/SRC2 SRC[7:3], [11:9] Ordering Information Part / Order Number Shipping Packaging Package T emperature C V183 -2 BP AG Tu bes 64-pin TSSOP 0 to +70° C CV 183 -2 BPA G8 Tape and Reel 64-pin TSSOP 0 to +70° C CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support: IDTCV183-2B PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR May 11, 2011 RDW Created/updated -2B datasheet. COMMERCIAL TEMPERATURE RANGE

PDF Datasheet Preview

IDTCV183-2B PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

COMMERCIAL TEMPERATURE RANGE

PROGRAMMABLE FLEXPC CLOCK

IDTCV183-2B

FEATURES:
• Compliant with Intel CK505 Gen II spec
• One high precision PLL for CPU, SSC and N programming
• One high precision PLL for SRC, SSC and N programming
• One high precision PLL for SATA/PCI, and SSC
• One high precision PLL for 96MHz/48MHz
• Push-pull IOs for differential outputs
• Support spread spectrum modulation, down spread and
others
• Support SMBus block read/write, byte read/write
• Available in TSSOP package

KEY FEATURES
• Internal serial resistor can be enabled by SMBus control register B19b7 to save the board space and material cost
• Direct CPU and SRC clock frequency the Hex number into Byte [16:18], 1 MHz stepping.
• Linear and smooth transition for the CPU and SRC frequency programming.
• Four Power On hardware modes see page 6, CFG configuration table
• CV183-2 When CFG[1:0] = 11, SATA clock power on default is from SRC PLL.

OUTPUTS:
• 2*0.7V differential CPU CLK pair
• 10*0.7V differential SRC CLK pair
• One CPU_ITP/SRC differential clock pair
• One SRC0/DOT96 differential clock pair
• 6*PCI, 33.3MHz
• 1*48MHz
• 1*REF
• 1*SATA

KEY SPECIFICATIONS:
• CPU/SRC CLK cycle to cycle jitter < 85ps
• PCI CLK cycle to cycle jitter < 500ps
• All SRC, SRC[0:11] phase noise < 3.10s RMS, PCIE Gen II
• SRC3, 4, 6, 7, designated PCIE Gen II outputs, nominal
interpair skew = 0 ps

FUNCTIONAL BLOCK DIAGRAM

XTAL_IN XTAL_OUT

SDATA SCLK

XTAL Osc Amp

SM Bus Controller

CKPWRGD/PD# CPU_STOP# PCI_STOP#

SRC5_EN, TME ITP_EN

CR_[H:A]# FSC,B,A

Control Logic

PLL1 SSC N Programmable

PLL3 SSC

PLL4 SSC N Programmable

Fixed PLL PLL2

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE
2011 Integrated Device Technology, Inc.

CPU Output Buffer

Stop Logic

PCI/SATA SRC CLK Output Buffer Stop Logic

SRC CLK Output Buffer

Stop Logic
48MHz/96MHz Output BUffer

REF CPU[1:0] CPU_ITP/SRC8 SRC1/SE PCI[4:0], PCIF5 SATA/SRC2 SRC[7:3], [11:9]
Ordering Information

Part / Order Number Shipping Packaging Package T emperature

C V183 -2 BP AG

Tu bes
64-pin TSSOP 0 to +70° C

CV 183 -2 BPA G8

Tape and Reel
64-pin TSSOP 0 to +70° C

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support:

IDTCV183-2B PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR

May 11, 2011

RDW Created/updated -2B datasheet.

COMMERCIAL TEMPERATURE RANGE

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDTCV183-2BPAG Datasheet file may be downloaded here without warranties.

Datasheet ID: IDTCV183-2BPAG 637407