IDT79RC32V134-DS

IDT79RC32V134-DS Datasheet

IDT79RC32134

Part	Datasheet
IDT79RC32V134-DS	IDT79RC32V134-DS (pdf)

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RISCore32300TM Family System Controller Chip IDT79RC32134 RC32300-family System Controller Direct connection between RC32364 and RC32134 Up to 75 MHz operation Drives latched address bus to memory and peripherals Direct control of optional external data buffers Programmable system watch-dog timers Big or Little endian support Interrupt Control Provides services for internal and external sources Allows status of each interrupt to be read and masked Three general purpose 32-bit timer/counters Programmable IO PIO Input/Output/Interrupt source Individually programmable SDRAM/EDODRAM Controller 32-bit memory only 4 banks, non-interleaved, 256 MB total Automatic refresh generation UART Interface Two 16550 Compatible UARTs Baud rate support up to 1.5M 8/16/32-bit boot PROM support Boundary Scan JTAG Interface IEEE Std. compatible Memory & Peripheral Controller 6 banks, up to 8MB per bank 8/16/ or 32-bit interface per bank Supports Flash ROM, SRAM, dual-port memory, and periph- eral devices Intel or Motorola style IO supports external wait-state genera- tion 4 DMA Channels 4 general purpose DMA, each with Endianness swappers and byte lane data alignment Any channel can be used for PCI Supports memory-to-memory, memory-to-I/O,memory-to- PCI, PCI-to-PCI, I/O-to-I/O transfers, and I/O support of scatter/gather Supports chaining via linked lists of records Supports unaligned transfers Supports burst transfers Programmable burst size PCI Bridge registers 3.3V core operation 3.3V I/O operation with 5V tolerant I/O 208 pin PQFP package Block Diagram Timer, UART, Interrupt Modules DMA Channels RC32134 CPU I/F PCI I/F and Bridge EDO/SDRAM Control Memory I/O Control Data & Address bus SDRAM/EDODRAM Control Memory & I/O Control PCI Bus The IDT logo is a registered trademark. RC64145, RC64474, RC64475, RC32134, RC4600, RC4640, RC4650, RC4700, RC3041, RC3051, RC3052, RC3081, RISController, and RISCore are trademarks of Integrated Device Technology, Inc. 2000 Integrated Device Technology, Inc. 1 of 25 April 9, 2001 DSC 5602 IDT79RC32134 The IDT79RC32134 is a high performance system controller chip that supports IDT’s RISCore32300 CPU family. The RC32134 offers a direct connection to IDT’s RC32364 32-bit embedded microprocessor. The RC32134 provides the system logic for boot memory, main memory, I/O, and PCI. It also includes on-chip peripherals such as DMA channels, reset circuitry, interrupts, timers, and UARTs. Together, the RC32364 CPU and the RC32134 system controller form a complete CPU subsystem for embedded designs. Figure 1 illustrates the typical system implementation, based on the RC32364 CPU and the RC32134 system controller. The RC32134 interfaces directly to the RC32364 and provides all of the necessary control and address signals to drive the external memory and I/O. Note that, depending on the loading of the CPU data bus, external data buffers could be used to reduce the loading and isolate different memory regions. As illustrated in the system block diagram, the memory and I/O data path is external to the RC32134. Memory Address Bus These signals provide the Memory or DRAM address, during a Memory or DRAM bus transactiion. During each word data, the address increments either in linear or sub-block ordering, depending on the transaction type. For 32-bit system, use mem_addr[3:2] for the least significant address bits For 8 or 16-bit wide ports, to provide the least significant address bits [3:0], use cpu_addr[3:2] and cpu_be_n[1:0]. mem_addr subsets mem_addr[22:20] I/O reset_boot_mode[1:0] reset_pci_host_mode mem_addr[15:2] I/O sdram_addr[15:13] sdram_addr[11:2] edodram_addr[15:2] mem_cs_n[5:0] Not applicable Memory Chip Select Negated This active-low signal indicates that a Memory or I/O Bank is actively selected. Table 2 RC32134 Pin Descriptions Page 4 of 8 8 of 25 April 9, 2001 IDT79RC32134 Pin Name Type Alternate Signal s mem_oe_n mem_we_n[3:0] mem_wait_n mem_245_oe_n mem_245_dt_r_n O EDODRAM Controller edodram_addr[15:2] O edodram_ras_n[3:0] O edodram_cas_n[3:0] O edodram_oe_n edodram_we_n edodram_wait_n Not applicable Not applicable edo_dram_wait_n Not applicable cpu_dt_r_n Memory Output Enable Negated This active-low signal indicates that either a Memory or I/O Bank can output its data lines onto the cpu_ad bus. Memory Write Enable Negated Bus These active-low signals indicate which bytes are to be written during a memory or I/O transaction. Memory Wait Negated In MEM, IOI, IOM modes this active-low signal allows external wait-states to be injected during the last cycle before data is sampled. In DPM dual-port mode, this signal allows dual-port busy signal to restart memory transaction. Memory FCT245 Output Enable Negated This active-low signal controls output enable to optional FCT245 transceiver bank by asserting during both reads and writes to a memory or I/O bank. Memory FCT245 Direction Xmit/Rcv Negated Uses the cpu_dt_r_n pin. mem_addr[15:2] sdram_cs_n[3:0] sdram_bemask_n[3:0] sdram_ras_n, sdram_245_oe_n sdram_we_n mem_wait_n Edodram_addr/sdram_addr mode These are output signals that provide a DRAM address during a DRAM transaction. The DRAM address multiplexes between Row and Column Addresses. During each word data, the column address increments either in linear or sub-block ordering, depending on the type of transaction. Allows an external memory debug emulator to inject wait-states. For more detail, see the user’s manual. DRAM Row Address Strobe Negated Bus SDRAM mode Provides chip select to each SDRAM bank. EDODRAM mode Used as edodram_ras_n[3:0] pins to provide a RAS signal for each EDODRAM bank. DRAM Column Address Strobe Negated Bus In the EDODRAM mode these signals are used as edodram_cas_n[3:0] to provide a CAS signal for each byte lane. In the SDRAM mode, these signals provide byte enables for each byte lane of all DRAM banks. DRAM EDO Output Enable Negated In the EDODRAM mode, this active-low signal provides an output enable signal for reads for particular OE types of EDODRAM. This signal also controls the output enable to an optional FCT245 transceiver bank by asserting during both reads and writes to any DRAM bank. This signal also controls the output enable to each EDO DRAM chip. Alternatively, because the EDODRAM controller always uses Early Writes and CAS controlled non-interleaved Reads, the OE_n pin, on each EDO DRAM chip, can simply be tied to ground. The SDRAM RAS mode is a control signal to all SDRAM banks. In SDRAM mode, this signal controls the output enable to an optional FCT245 transceiver bank by asserting during both reads and writes to any DRAM bank. DRAM EDO Write Enable Negated In EDODRAM mode, this active-low signal is used as the edodram_we_n pin to provide a write enable signal for EDODRAM. Write enable is valid at all times and high during refresh. In SDRAM mode, this signal provides the SDRAM WE control signal to all SDRAM banks. DRAM Wait Negated In the EDO DRAM mode, this active-low signal allows external wait-states to be injected at any time during the EDO DRAM cycle. In the MEM, IOI, IOM modes, this active-low signal allows external wait-states to be injected during the last cycle before data is sampled. The DPM dual-port mode allows the dual-port busy signal to restart memory transactions. Table 2 RC32134 Pin Descriptions Page 5 of 8 9 of 25 April 9, 2001 IDT79RC32134 Pin Name Type Alternate Signal s edodram_245_oe_n O sdram_245_oe_n edodram_245_dt_r_n O cpu_dt_r_n SDRAM Controller Interface sdram_addr[15:13] O sdram_addr[11:2] mem_addr[15:13] mem_addr[11:2] sdram_addr_12 PIO[9] sdram_ras_n edodram_oe_n sdram_cas_n sdram_we_n Not applicable edodram_we_n sdram_clk cpu_masterclk sdram_cke sdram_cs_n[3:0] Not applicable edodram_ras_n[3:0] sdram_bemask_n[3:0] O edodram_cas_n[3:0] sdram_245_oe_n O edodram_245_oe_n, edodram_oe_n DRAM FCT245 Output Enable Negated In the SDRAM mode this active-low signal controls the output enable to an optional FCT245 transceiver bank by asserting during both reads and writes to any DRAM bank. In the EDODRAM mode this signal controls the output enable to an optional FCT245 transceiver bank by asserting during both reads and writes to any DRAM bank. This signal also controls the output enable to each EDO DRAM chip. Alternatively, because the EDODRAM controller always uses Early Writes and CAS controlled non-interleaved Reads, the OE_n pin, on each EDO DRAM chip, can simply be tied to ground. DRAM/Mem FCT245 Direct Xmit/Rcv Negated This active-low signal controls the DT/R pin of an optional FCT245 transceiver bank. It is asserted during DMA read operations. This signal is tri-stated during CPU accesses when the CPU owns the bus and drives during DMA generated accesses. SDRAM Address Bus These signals are outputs providing a DRAM address during a DRAM transaction. The DRAM address multiplexes between Row and Column Addresses. During each word data, the column address increments either in linear or sub-block ordering, depending on the type of transaction. SDRAM Address line 12 This SDRAM address is dedicated to the SDRAM and multiplexes between the row address and during the precharge command, the "all bank" indicator. SDRAM RAS Negated SDRAM mode Provides SDRAM RAS control signal to all SDRAM banks. EDODRAM mode Provides an output enable signal for reads for particular OE types of EDODRAM. SDRAM CAS Negated This active-low signal provides an SDRAM CAS control signal to all SDRAM banks. SDRAM WE Negated SDRAM mode Provides SDRAM WE control signal to all SDRAM banks. EDODRAM mode Used as edodram_we_n pin to provide a write enable signal for EDODRAM. Write enable is valid at all times and high during refresh. SDRAM Clock This signal provides the basic system clock and must be the same clock that is provided to the RC32364 and also, if used, to SDRAM. SDRAM Clock Enable In the SDRAM mode this signal provides the clock enable to all SDRAM banks. SDRAM Chip Select Negated Bus In SDRAM mode, these active-low signals provide chip select to each SDRAM bank. In EDODRAM mode they are used as the edodram_ras_n[3:0] pins and provide a RAS signal for each EDODRAM bank. SDRAM Byte Enable Mask Negated Bus The SDRAM mode provides byte enables for each byte lane of all DRAM banks. To provide a CAS signal for each byte lane, the EDODRAM mode is used as edodram_cas_n[3:0]. SDRAM FCT245 Output Enable Negated In SDRAM mode, this active-low signal controls output enable to optional FCT245 transceiver bank by asserting during both reads and writes to any DRAM bank. In EDODRAM mode this signal controls output enable to optional FCT245 transceiver bank by asserting during both reads and writes to any DRAM bank. Also controls output enable to each EDO DRAM chip. Alternatively, because the EDODRAM controller always uses Early Writes and CAS controlled non-interleaved Reads, the OE_n pin on each EDO DRAM chip can simply be tied to ground. Table 2 RC32134 Pin Descriptions Page 6 of 8 10 of 25 April 9, 2001 IDT79RC32134 Pin Name Type Alternate Signal s sdram_245_dt_r_n O DMA Interface dma_ready_n[1:0] I/O dma_done_n[1:0] I/O Interrupt Controller interrupt_n PIO Interface pio[11:0] Timer/Counter timer_tc_n[1:0] timer_gate_n[1:0] I UART Interface uart_rx[1:0] uart_tx[1:0] cpu_dt_r_n SDRAM FCT245 Direction Transmit/Receive This active-low signal controls the DT/R pin of an optional FCT245 transceiver bank and is asserted during DMA read operations. This signal is tri-stated during CPU accesses when the CPU owns the bus and drives during DMA generated accesses. dma_done_n[1:0] pio[1:0] dma_ready_n[1:0] DMA Ready Negated Bus Input pin for general purpose DMA channels[1:0] that can initiate the next datum in the current DMA descriptor frame. dma_ready_n[1:0] pins are not synchronized internally by the RC32134 and thus must meet the specified setup and hold time with respect to the input clock. DMA Done Input pin for general purpose DMA channels[1:0] that can terminate the current DMA descriptor frame. cpu_int_n Interrupt Negated Uses cpu_int_n. This active-low signal is an interrupt indication to the CPU from RC32134’s Interrupt Controller. pci_eeprom_mdo pci_eeprom_sk sdram_addr_12 pci_eeprom_mdi uart _rx[0], uart_tx[0] uart_rx[1], uart_tx[1] timer_tc_n[0], timer_tc_n[1] dma_ready_n[0] dma_ready_n[1] Programmable Input/Output General purpose pins that can each be configured as a general purpose input or general purpose output. The pci_eeprom_mdo, pci_eeprom_sk, and sdram_addr12 default to outputs. The rest default to inputs. timer_gate_n[1:0], pio[3:2] timer_tc_n[1:0], pio[3:2] Timer Terminal Count Overflow Negated Output indicating that the timer has reached its count compare value and has overflowed back to Timer Gate Negated Input indicating that the timer may count one tick on the next clock edge. Ordering Information IDT79RCXX V Product Type Operating Voltage Device Type PP Package Temp range/ Process blank = Commercial Temperature 0°C to +90°C Case I = Industrial Temperature -40°C to +90°C Case DS = 208-pin PQFP 134 = 32134 System Controller V = 3.3V ±5% IDT79RC32 = 32-bit family product Valid Combinations IDT79RC32V134 DS 208-pin PQFP package - Commercial Temperature IDT79RC32V134 DSI 208-pin PQFP package - Industrial Temperature CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 The IDT logo is a trademark of Integrated Device Technology, Inc. 25 of 25 for Tech Support email phone 408-284-8208 April 9, 2001

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RISCore32300TM Family System Controller Chip

IDT79RC32134

RC32300-family System Controller Direct connection between RC32364 and RC32134 Up to 75 MHz operation Drives latched address bus to memory and peripherals Direct control of optional external data buffers Programmable system watch-dog timers Big or Little endian support

Interrupt Control Provides services for internal and external sources Allows status of each interrupt to be read and masked

Three general purpose 32-bit timer/counters

Programmable IO PIO Input/Output/Interrupt source Individually programmable

SDRAM/EDODRAM Controller 32-bit memory only 4 banks, non-interleaved, 256 MB total Automatic refresh generation

UART Interface Two 16550 Compatible UARTs Baud rate support up to 1.5M
8/16/32-bit boot PROM support

Boundary Scan JTAG Interface IEEE Std. compatible

Memory & Peripheral Controller 6 banks, up to 8MB per bank
8/16/ or 32-bit interface per bank Supports Flash ROM, SRAM, dual-port memory, and periph-
eral devices Intel or Motorola style IO supports external wait-state genera-
tion
4 DMA Channels
4 general purpose DMA, each with Endianness swappers and byte lane data alignment

Any channel can be used for PCI Supports memory-to-memory, memory-to-I/O,memory-to-

PCI, PCI-to-PCI, I/O-to-I/O transfers, and I/O support of scatter/gather Supports chaining via linked lists of records Supports unaligned transfers Supports burst transfers Programmable burst size

PCI Bridge
registers
3.3V core operation
3.3V I/O operation with 5V tolerant I/O
208 pin PQFP package

Block Diagram

Timer, UART, Interrupt Modules

DMA Channels

RC32134

CPU I/F PCI I/F and Bridge

EDO/SDRAM Control

Memory I/O Control

Data & Address bus

SDRAM/EDODRAM Control Memory & I/O Control

PCI Bus

The IDT logo is a registered trademark. RC64145, RC64474, RC64475, RC32134, RC4600, RC4640, RC4650, RC4700, RC3041, RC3051, RC3052, RC3081, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
2000 Integrated Device Technology, Inc.
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April 9, 2001

DSC 5602

IDT79RC32134

The IDT79RC32134 is a high performance system controller chip that supports IDT’s RISCore32300 CPU family. The RC32134 offers a direct connection to IDT’s RC32364 32-bit embedded microprocessor. The RC32134 provides the system logic for boot memory, main memory, I/O, and PCI. It also includes on-chip peripherals such as DMA channels, reset circuitry, interrupts, timers, and UARTs. Together, the RC32364 CPU and the RC32134 system controller form a complete CPU subsystem for embedded designs.

Figure 1 illustrates the typical system implementation, based on the RC32364 CPU and the RC32134 system controller. The RC32134 interfaces directly to the RC32364 and provides all of the necessary control and address signals to drive the external memory and I/O. Note that, depending on the loading of the CPU data bus, external data buffers could be used to reduce the loading and isolate different memory regions. As illustrated in the system block diagram, the memory and I/O data path is external to the RC32134.
Memory Address Bus These signals provide the Memory or DRAM address, during a Memory or DRAM bus transactiion. During each word data, the address increments either in linear or sub-block ordering, depending on the transaction type. For 32-bit system, use mem_addr[3:2] for the least significant address bits For 8 or 16-bit wide ports, to provide the least significant address bits [3:0], use cpu_addr[3:2] and cpu_be_n[1:0].
mem_addr subsets
mem_addr[22:20] I/O
reset_boot_mode[1:0] reset_pci_host_mode
mem_addr[15:2] I/O
sdram_addr[15:13] sdram_addr[11:2] edodram_addr[15:2]
mem_cs_n[5:0]

Not applicable

Memory Chip Select Negated This active-low signal indicates that a Memory or I/O Bank is actively selected.

Table 2 RC32134 Pin Descriptions Page 4 of 8
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IDT79RC32134

Pin Name Type Alternate Signal s
mem_oe_n
mem_we_n[3:0]
mem_wait_n
mem_245_oe_n
mem_245_dt_r_n O

EDODRAM Controller edodram_addr[15:2] O
edodram_ras_n[3:0] O
edodram_cas_n[3:0] O
edodram_oe_n
edodram_we_n
edodram_wait_n

Not applicable Not applicable edo_dram_wait_n

Not applicable cpu_dt_r_n

Memory Output Enable Negated This active-low signal indicates that either a Memory or I/O Bank can output its data lines onto the cpu_ad bus.

Memory Write Enable Negated Bus These active-low signals indicate which bytes are to be written during a memory or I/O transaction.

Memory Wait Negated In MEM, IOI, IOM modes this active-low signal allows external wait-states to be injected during the last cycle before data is sampled. In DPM dual-port mode, this signal allows dual-port busy signal to restart memory transaction.

Memory FCT245 Output Enable Negated This active-low signal controls output enable to optional FCT245 transceiver bank by asserting during both reads and writes to a memory or I/O bank.

Memory FCT245 Direction Xmit/Rcv Negated Uses the cpu_dt_r_n pin.
mem_addr[15:2]
sdram_cs_n[3:0] sdram_bemask_n[3:0] sdram_ras_n, sdram_245_oe_n
sdram_we_n mem_wait_n
Edodram_addr/sdram_addr mode These are output signals that provide a DRAM address during a DRAM transaction. The DRAM address multiplexes between Row and Column Addresses. During each word data, the column address increments either in linear or sub-block ordering, depending on the type of transaction. Allows an external memory debug emulator to inject wait-states. For more detail, see the user’s manual.

DRAM Row Address Strobe Negated Bus SDRAM mode Provides chip select to each SDRAM bank. EDODRAM mode Used as edodram_ras_n[3:0] pins to provide a RAS signal for each EDODRAM bank.

DRAM Column Address Strobe Negated Bus In the EDODRAM mode these signals are used as edodram_cas_n[3:0] to provide a CAS signal for each byte lane. In the SDRAM mode, these signals provide byte enables for each byte lane of all DRAM banks.

DRAM EDO Output Enable Negated In the EDODRAM mode, this active-low signal provides an output enable signal for reads for particular OE types of EDODRAM. This signal also controls the output enable to an optional FCT245 transceiver bank by asserting during both reads and writes to any DRAM bank. This signal also controls the output enable to each EDO DRAM chip. Alternatively, because the EDODRAM controller always uses Early Writes and CAS controlled non-interleaved Reads, the OE_n pin, on each EDO DRAM chip, can simply be tied to ground. The SDRAM RAS mode is a control signal to all SDRAM banks. In SDRAM mode, this signal controls the output enable to an optional FCT245 transceiver bank by asserting during both reads and writes to any DRAM bank.

DRAM EDO Write Enable Negated In EDODRAM mode, this active-low signal is used as the edodram_we_n pin to provide a write enable signal for EDODRAM. Write enable is valid at all times and high during refresh. In SDRAM mode, this signal provides the SDRAM WE control signal to all SDRAM banks.

DRAM Wait Negated In the EDO DRAM mode, this active-low signal allows external wait-states to be injected at any time during the EDO DRAM cycle. In the MEM, IOI, IOM modes, this active-low signal allows external wait-states to be injected during the last cycle before data is sampled. The DPM dual-port mode allows the dual-port busy signal to restart memory transactions.

Table 2 RC32134 Pin Descriptions Page 5 of 8
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IDT79RC32134

Pin Name Type Alternate Signal s
edodram_245_oe_n O
sdram_245_oe_n
edodram_245_dt_r_n O
cpu_dt_r_n

SDRAM Controller Interface
sdram_addr[15:13] O sdram_addr[11:2]
mem_addr[15:13] mem_addr[11:2]
sdram_addr_12

PIO[9]
sdram_ras_n
edodram_oe_n
sdram_cas_n sdram_we_n

Not applicable
edodram_we_n
sdram_clk
cpu_masterclk
sdram_cke
sdram_cs_n[3:0]

Not applicable edodram_ras_n[3:0]
sdram_bemask_n[3:0] O
edodram_cas_n[3:0]
sdram_245_oe_n O
edodram_245_oe_n, edodram_oe_n

DRAM FCT245 Output Enable Negated In the SDRAM mode this active-low signal controls the output enable to an optional FCT245 transceiver bank by asserting during both reads and writes to any DRAM bank. In the EDODRAM mode this signal controls the output enable to an optional FCT245 transceiver bank by asserting during both reads and writes to any DRAM bank. This signal also controls the output enable to each EDO DRAM chip. Alternatively, because the EDODRAM controller always uses Early Writes and CAS controlled non-interleaved Reads, the OE_n pin, on each EDO DRAM chip, can simply be tied to ground.

DRAM/Mem FCT245 Direct Xmit/Rcv Negated This active-low signal controls the DT/R pin of an optional FCT245 transceiver bank. It is asserted during DMA read operations. This signal is tri-stated during CPU accesses when the CPU owns the bus and drives during DMA generated accesses.
SDRAM Address Bus These signals are outputs providing a DRAM address during a DRAM transaction. The DRAM address multiplexes between Row and Column Addresses. During each word data, the column address increments either in linear or sub-block ordering, depending on the type of transaction.

SDRAM Address line 12 This SDRAM address is dedicated to the SDRAM and multiplexes between the row address and during the precharge command, the "all bank" indicator.

SDRAM RAS Negated SDRAM mode Provides SDRAM RAS control signal to all SDRAM banks. EDODRAM mode Provides an output enable signal for reads for particular OE types of EDODRAM.

SDRAM CAS Negated This active-low signal provides an SDRAM CAS control signal to all SDRAM banks.

SDRAM WE Negated SDRAM mode Provides SDRAM WE control signal to all SDRAM banks. EDODRAM mode Used as edodram_we_n pin to provide a write enable signal for EDODRAM. Write enable is valid at all times and high during refresh.

SDRAM Clock This signal provides the basic system clock and must be the same clock that is provided to the RC32364 and also, if used, to SDRAM.

SDRAM Clock Enable In the SDRAM mode this signal provides the clock enable to all SDRAM banks.

SDRAM Chip Select Negated Bus In SDRAM mode, these active-low signals provide chip select to each SDRAM bank. In EDODRAM mode they are used as the edodram_ras_n[3:0] pins and provide a RAS signal for each EDODRAM bank.

SDRAM Byte Enable Mask Negated Bus The SDRAM mode provides byte enables for each byte lane of all DRAM banks. To provide a CAS signal for each byte lane, the EDODRAM mode is used as edodram_cas_n[3:0].

SDRAM FCT245 Output Enable Negated In SDRAM mode, this active-low signal controls output enable to optional FCT245 transceiver bank by asserting during both reads and writes to any DRAM bank. In EDODRAM mode this signal controls output enable to optional FCT245 transceiver bank by asserting during both reads and writes to any DRAM bank. Also controls output enable to each EDO DRAM chip. Alternatively, because the EDODRAM controller always uses Early Writes and CAS controlled non-interleaved Reads, the OE_n pin on each EDO DRAM chip can simply be tied to ground.

Table 2 RC32134 Pin Descriptions Page 6 of 8
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IDT79RC32134

Pin Name Type Alternate Signal s
sdram_245_dt_r_n O

DMA Interface dma_ready_n[1:0] I/O
dma_done_n[1:0] I/O

Interrupt Controller
interrupt_n

PIO Interface
pio[11:0]

Timer/Counter
timer_tc_n[1:0]
timer_gate_n[1:0] I

UART Interface
uart_rx[1:0]
uart_tx[1:0]
cpu_dt_r_n

SDRAM FCT245 Direction Transmit/Receive This active-low signal controls the DT/R pin of an optional FCT245 transceiver bank and is asserted during DMA read operations. This signal is tri-stated during CPU accesses when the CPU owns the bus and drives during DMA generated accesses.
dma_done_n[1:0] pio[1:0]
dma_ready_n[1:0]

DMA Ready Negated Bus Input pin for general purpose DMA channels[1:0] that can initiate the next datum in the current DMA descriptor frame. dma_ready_n[1:0] pins are not synchronized internally by the RC32134 and thus must meet the specified setup and hold time with respect to the input clock.

DMA Done Input pin for general purpose DMA channels[1:0] that can terminate the current DMA descriptor frame.
cpu_int_n

Interrupt Negated Uses cpu_int_n. This active-low signal is an interrupt indication to the CPU from RC32134’s Interrupt Controller.
pci_eeprom_mdo pci_eeprom_sk sdram_addr_12 pci_eeprom_mdi uart _rx[0], uart_tx[0] uart_rx[1], uart_tx[1] timer_tc_n[0], timer_tc_n[1] dma_ready_n[0] dma_ready_n[1]

Programmable Input/Output General purpose pins that can each be configured as a general purpose input or general purpose output. The pci_eeprom_mdo, pci_eeprom_sk, and sdram_addr12 default to outputs. The rest default to inputs.
timer_gate_n[1:0], pio[3:2] timer_tc_n[1:0], pio[3:2]

Timer Terminal Count Overflow Negated Output indicating that the timer has reached its count compare value and has overflowed back to

Timer Gate Negated Input indicating that the timer may count one tick on the next clock edge.
Ordering Information

IDT79RCXX V

Product Type

Operating Voltage

Device Type

PP Package

Temp range/ Process
blank = Commercial Temperature 0°C to +90°C Case I = Industrial Temperature -40°C to +90°C Case DS = 208-pin PQFP 134 = 32134 System Controller

V = 3.3V ±5%

IDT79RC32 = 32-bit family product

Valid Combinations

IDT79RC32V134 DS
208-pin PQFP package - Commercial Temperature

IDT79RC32V134 DSI
208-pin PQFP package - Industrial Temperature

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775

The IDT logo is a trademark of Integrated Device Technology, Inc.
25 of 25
for Tech Support email phone 408-284-8208

April 9, 2001

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT79RC32V134-DS Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT79RC32V134-DS 637385