IDT74LVC16823APAG8

IDT74LVC16823APAG8 Datasheet

IDT74LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS

Part	Datasheet
IDT74LVC16823APAG8	IDT74LVC16823APAG8 (pdf)

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IDT74LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE IDT74LVC16823A FEATURES: • Typical tSK o Output Skew < 250ps • ESD > 2000V per MIL-STD-883, Method 3015 > 200V using machine model C = 200pF, R = 0 • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • CMOS power levels W typ. static • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in SSOP and TSSOP packages DRIVE FEATURES: • High Output Drivers ±24mA • Reduced system switching noise APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems DESCRIPTION: The LVC16823A 18-bit register is built using advanced dual metal CMOS technology. This high-speed, low-power register is ideal for use as a buffer register for data synchronization and storage. The Output Enable OE and clock CLK controls are organized to operate each device as two 9-bit registers or one 18-bit register with common clock. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. All pins of the LVC16823A can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/ 5V supply system. The LVC16823A has been designed with a ±24mA output driver. The driver is capable of driving a moderate to heavy load while maintaining speed performance. FUNCTIONAL BLOCK DIAGRAM 1OE 1CLR 1 1CLK 1CLKEN 2OE 2CLR 28 2CLK 29 2CLKEN 3 1Q1 2D1 42 15 2Q1 TO EIGHT OTHER CHANNELS TO EIGHT OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 2006 Integrated Device Technology, Inc. February 20, 2009 DSC-4573/6 IDT74LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS PIN CONFIGURATION 1CLR GND 11 GND 18 2CLR 1CLK 1CLKEN 46 GND ORDERING INFORMATION LVC X XXXX Temp. Range Bus-Hold Family Device Type Package INDUSTRIAL TEMPERATURE RANGE PV PVG PA PAG Shrink Small Outline Package SSOP - Green Thin Shrink Small Outline Package TSSOP - Green 823A 18-Bit Register with 3-State Outputs 16 Double-Density, ±24mA Blank No Bus-hold 74 -40°C to +85°C CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support:

PDF Datasheet Preview

IDT74LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS
3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O

INDUSTRIAL TEMPERATURE RANGE

IDT74LVC16823A

FEATURES:
• Typical tSK o Output Skew < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015 > 200V using
machine model C = 200pF, R = 0
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels W typ. static
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP and TSSOP packages

DRIVE FEATURES:
• High Output Drivers ±24mA
• Reduced system switching noise

APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems

DESCRIPTION:

The LVC16823A 18-bit register is built using advanced dual metal CMOS technology. This high-speed, low-power register is ideal for use as a buffer register for data synchronization and storage. The Output Enable OE and clock CLK controls are organized to operate each device as two 9-bit registers or one 18-bit register with common clock. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin.

All pins of the LVC16823A can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/ 5V supply system.

The LVC16823A has been designed with a ±24mA output driver. The driver is capable of driving a moderate to heavy load while maintaining speed performance.

FUNCTIONAL BLOCK DIAGRAM
1OE 1CLR 1
1CLK
1CLKEN
2OE 2CLR 28
2CLK 29
2CLKEN
3 1Q1
2D1 42
15 2Q1

TO EIGHT OTHER CHANNELS

TO EIGHT OTHER CHANNELS

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE
2006 Integrated Device Technology, Inc.

February 20, 2009

DSC-4573/6

IDT74LVC16823A 3.3V CMOS 18-BIT REGISTER WITH 3-STATE OUTPUTS

PIN CONFIGURATION
1CLR

GND 11

GND 18
2CLR
1CLK
1CLKEN
46 GND
ORDERING INFORMATION

LVC X

XXXX

Temp. Range Bus-Hold Family Device Type Package

INDUSTRIAL TEMPERATURE RANGE

PV PVG PA PAG

Shrink Small Outline Package SSOP - Green Thin Shrink Small Outline Package TSSOP - Green
823A 18-Bit Register with 3-State Outputs
16 Double-Density, ±24mA

Blank No Bus-hold
74 -40°C to +85°C

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT74LVC16823APAG8 Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT74LVC16823APAG8 637376