IDT72V3682L10PF8

IDT72V3682L10PF8 Datasheet

IDT72V3682 IDT72V3692 IDT72V36102

Part	Datasheet
IDT72V3682L10PF8	IDT72V3682L10PF8 (pdf)

Related Parts	Information
IDT72V36102L10PFG8	IDT72V36102L10PFG8
IDT72V36102L10PF	IDT72V36102L10PF
IDT72V36102L10PF8	IDT72V36102L10PF8
IDT72V36102L10PFG	IDT72V36102L10PFG
IDT72V36102L15PF8	IDT72V36102L15PF8
IDT72V36102L15PF	IDT72V36102L15PF
IDT72V3682L15PF	IDT72V3682L15PF
IDT72V3682L15PF8	IDT72V3682L15PF8
IDT72V3682L10PFG	IDT72V3682L10PFG
IDT72V3682L15PFGI	IDT72V3682L15PFGI
IDT72V3682L10PF	IDT72V3682L10PF

PDF Datasheet Preview
VOLT CMOS SyncBiFIFOTM 16,384 x 36 x 2 32,768 x 36 x 2 65,536 x 36 x 2 IDT72V3682 IDT72V3692 IDT72V36102 • Memory storage capacity IDT72V3682 16,384 x 36 x 2 IDT72V3692 32,768 x 36 x 2 IDT72V36102 65,536 x 36 x 2 • Supports clock frequencies up to 100MHz • Fast access times of 6.5ns • Free-running CLKA and CLKB may be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted • Two independent clocked FIFOs buffering data in opposite directions • Mailbox bypass register for each FIFO • Programmable Almost-Full and Almost-Empty flags • Microprocessor Interface Control Logic • FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA • FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB • Select IDT Standard timing using EFA, EFB, FFA and FFB flags functions or First Word Fall Through timing using ORA, ORB, IRA and IRB flag functions • Available in space-saving 120-pin Thin Quad Flatpack TQFP • Pin compatible to the lower density parts, IDT72V3622/72V3632/ 72V3642/72V3652/72V3662/72V3672 • Industrial temperature range to +85°C is available • Green parts available, see ordering information FUNCTIONAL BLOCK DIAGRAM CLKA CSA W/RA ENA MBA Port-A Control Logic RST1 FIFO1, Mail1 Reset Logic Mail 1 Register RAM ARRAY 16,384 x 36 32,768 x 36 65,536 x 36 Write Pointer Read Pointer Input Register Output Register MBF1 FFA/IRA AFA FIFO 1 Status Flag Logic EFB/ORB AEB FS0 FS1 A0 - A35 EFA/ORA AEA MBF2 Programmable Flag Timing Offset Registers Mode FIFO 2 Status Flag Logic Read Write Pointer Pointer ARRAY 16,384 x 36 32,768 x 36 65,536 x 36 Mail 2 Register Output Register Input Register FWFT B0 - B35 FFB/IRB AFB FIFO2, Mail2 Reset Logic RST2 Port-B Control Logic CLKB CSB W/RB ENB MBB 4679 drw 01 ORDERING INFORMATION Device Type Power Speed Package Process/ Temperature Range BLANK Commercial 0oC to +70oC Green Thin Quad Flat Pack TQFP, PN120-1 10 15 Commercial Only Clock Cycle Time tCLK Speed in Nanoseconds Low Power NOTES Industrial temperature range is available by special order. Green parts available. For specific speeds and packages contact your sales office. 72V3682 16,384 x 36 x 2 3.3V SyncBiFIFO 72V3692 32,768 x 36 x 2 3.3V SyncBiFIFO 72V36102 65,536 x 36 x 2 3.3V SyncBiFIFO 4679 drw26 DATASHEET DOCUMENT HISTORY 10/30/2000 03/27/2001 11/04/2003 05/23/2008 02/04/2009 pgs. 1, 2, 3, 6, 8, 9, 11 and pgs. 6 and pg. pgs. 1, 6, and pg. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support 408-360-1753 email:

PDF Datasheet Preview

VOLT CMOS SyncBiFIFOTM 16,384 x 36 x 2 32,768 x 36 x 2 65,536 x 36 x 2

IDT72V3682 IDT72V3692 IDT72V36102
• Memory storage capacity IDT72V3682 16,384 x 36 x 2 IDT72V3692 32,768 x 36 x 2 IDT72V36102 65,536 x 36 x 2
• Supports clock frequencies up to 100MHz
• Fast access times of 6.5ns
• Free-running CLKA and CLKB may be asynchronous or coincident
simultaneous reading and writing of data on a single clock edge is permitted
• Two independent clocked FIFOs buffering data in opposite directions
• Mailbox bypass register for each FIFO
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor Interface Control Logic
• FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA
• FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB
• Select IDT Standard timing using EFA, EFB, FFA and FFB flags
functions or First Word Fall Through timing using ORA, ORB, IRA
and IRB flag functions
• Available in space-saving 120-pin Thin Quad Flatpack TQFP
• Pin compatible to the lower density parts, IDT72V3622/72V3632/
72V3642/72V3652/72V3662/72V3672
• Industrial temperature range to +85°C is available
• Green parts available, see ordering information

FUNCTIONAL BLOCK DIAGRAM

CLKA CSA

W/RA ENA MBA

Port-A Control Logic

RST1

FIFO1, Mail1 Reset Logic

Mail 1 Register

RAM ARRAY 16,384 x 36 32,768 x 36 65,536 x 36

Write Pointer

Read Pointer

Input Register Output Register

MBF1

FFA/IRA AFA

FIFO 1

Status Flag Logic

EFB/ORB AEB

FS0 FS1 A0 - A35 EFA/ORA AEA

MBF2

Programmable Flag Timing

Offset Registers

Mode

FIFO 2

Status Flag

Logic

Read

Write

Pointer

Pointer

ARRAY
16,384 x 36 32,768 x 36 65,536 x 36

Mail 2 Register

Output Register

Input Register

FWFT

B0 - B35 FFB/IRB AFB

FIFO2, Mail2 Reset Logic

RST2

Port-B Control Logic

CLKB CSB W/RB ENB MBB
4679 drw 01
ORDERING INFORMATION

Device Type Power Speed Package

Process/ Temperature

Range

BLANK Commercial 0oC to +70oC

Green

Thin Quad Flat Pack TQFP, PN120-1
10 15

Commercial Only

Clock Cycle Time tCLK Speed in Nanoseconds

Low Power

NOTES Industrial temperature range is available by special order. Green parts available. For specific speeds and packages contact your sales office.
72V3682 16,384 x 36 x 2 3.3V SyncBiFIFO 72V3692 32,768 x 36 x 2 3.3V SyncBiFIFO 72V36102 65,536 x 36 x 2 3.3V SyncBiFIFO
4679 drw26

DATASHEET DOCUMENT HISTORY
10/30/2000 03/27/2001 11/04/2003 05/23/2008 02/04/2009
pgs. 1, 2, 3, 6, 8, 9, 11 and pgs. 6 and pg. pgs. 1, 6, and pg.

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support 408-360-1753
email:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT72V3682L10PF8 Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT72V3682L10PF8 637359