IDT72T6480L7-5BBG

IDT72T6480L7-5BBG Datasheet

IDT72T6480

Part	Datasheet
IDT72T6480L7-5BBG	IDT72T6480L7-5BBG (pdf)

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IDT72T6480L7-5BB	IDT72T6480L7-5BB

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2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM IDT72T6480 • Product to be used with single or multiple external DDR SDRAM to provide significant storage capability of up to 1Gb density • 133MHz operation 7.5ns read/write cycle time • User selectable input and output port bus-sizing - x48in to x48out - x48in to x24out - x48in to x12out - x24in to x48out - x24in to x24out - x24in to x12out - x12in to x48out - x12in to x24out - x12in to x12out • For other bus configurations see IDT72T6360 x9, x18, or x36 • 2.5V-LVTTL or 3.3V-LVTTL configured ports • Independent and simultaneous read and write access • User selectable synchronous/asynchronous read and write port timing • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag can default to one of four preselected offsets or serially programmed to a specific value • Selectable synchronous/asynchronous timing modes for Almost-Empty and Almost-Full flags • Master Reset clears all data and settings • Partial Reset clears data, but retains programmable settings • Depth expandable with multiple devices for densities greater than 1Gb • Width expandable with multiple devices for bus widths greater than 36 bits • JTAG functionality Boundary Scan • Available in a 324-pin PBGA, 1mm pitch, 19mm x 19mm • HIGH performance 0.18µm CMOS technology • Industrial temperature range -40°C to +85°C is available • Supports industry standard DDR specifications, including Samsung, Micron, and Infineon memories FUNCTIONAL BLOCK DIAGRAM FWFT FSEL[1:0] FF/IR PAF EF/OR PAE Flag Logic x48, x24, or x12 IDT72T6480 Sequential Flow Control Device I/O Bus Reset Configuration Logic MRS PRS IOSEL BM[3:0] x48, x24, or x12 O3u6t-pbiuttsRegister 36-bits Write Control Logic Input Register WEN WCLK/WR WCS ASYW DDR SDRAM Control Logic CK DQS WE CAS RAS Addr JTAG Control Boundary Scan MCLK 64 13 36-bits Read Control Logic - Read Port Interface 7 - Write Port Interface 7 - Memory Interface 8 - Control and Feature Interface 8 - Power and Ground Signals 10 - Pin Number Location Table 10 Detailed Descriptions 11 Functional Descriptions 22 Signal Descriptions 23 Device Characteristics 27 AC Test Conditions 29 AC Electrical Characteristics 30 JTAG Timing Specifications 45 Depth Expansion Configuration 49 Width Expansion Configuration 50 Ordering Information 51 List of Tables Table 1 DDR SDRAM Minimum Specifications 11 Table 2 Supported Memory Vendors 11 Table 3 Total Possible External Memory Configurations 12 Table 4 SFC to DDR SDRAM interface Connections 14 Table 5 Total useable memory based on various configurations 18 Table 6 IDT72T6480 Maximum Frequency Based on 166MHz DDR SDRAM 19 Table 7 IDT72T6480 Maximum Frequency Based on 133MHz DDR SDRAM 19 Table 8 MIC[2:0] Configurations 20 Table 9 Memory Configurations Settings 21 Table 10 Device configuration 22 Table Default Programmable Flag Offsets 22 Table Number of Bits Required for Offset Registers 22 Table 13 Bus-Matchings 24 Table 14 MTYPE[1:0] Configurations 25 Table 15 Parameters affected by I/O selection 25 FEBRUARY 10, 2009 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION List of Figures COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Figure Sequential Flow-Control Device Block Diagram 5 Figure 2a. Configuration 1 - Two Chip Solution 13 Figure 2b. Configuration 2 - Two Chip Solution 13 Figure 2c. Configuration 3 - Three Chip Solution 13 Figure 2d. Configuration 4 - Three Chip Solution 13 Figure 2e. Configuration 5 - Three Chip Solution 13 Figure 2f. Configuration 6 - Four Chip Solution 13 Figure 2g. Configuration 7 - Five Chip Solution 13 Figure Memory Interface Connection Single Chip 17 Figure Memory Interface Connection Two Chip 17 Figure 5a. AC Test Load 29 Figure 5b. Lumped Capacitive Load, Typical Derating 29 Figure Master Reset and Initialization 32 Figure Partial Reset 33 Figure Write First Word Cycles - IDT Standard Mode 34 Figure Write First Word Cycles - FWFT Mode 34 Figure Empty Boundary - IDT Standard Mode 35 Figure Empty Boundary - FWFT Mode 35 Figure Full Boundary - IDT Standard Mode 36 Figure Full Boundary - FWFT Mode 36 Figure Output Enable 37 Figure Read Chip Select 37 Figure Write Chip Select 37 Figure Bus-Matching Configuration - x48 In to x24 Out - IDT Standard Mode 38 Figure Bus-Matching Configuration - x48 In to x12 Out - IDT Standard Mode 38 Figure Bus-Matching Configuration - x24 In to x48 Out - IDT Standard Mode 39 Figure Bus-Matching Configuration - x12 In to x48 Out - IDT Standard Mode 39 Figure Synchronous PAE Flag - IDT Standard Mode and FWFT Mode 40 Figure Synchronous PAF Flag - IDT Standard Mode and FWFT Mode 40 Figure Asynchronous Read and PAF Flag - IDT Standard Mode 41 Figure Asynchronous Write and PAE Flag - IDT Standard Mode 41 Figure Asynchronous Write and PAF Flag - IDT Standard Mode 41 Figure Asynchronous Empty Boundary - IDT Standard Mode 42 Figure Asynchronous Full Boundary - IDT Standard Mode 42 Figure Asynchronous Read and PAE Flag - IDT Standard Mode 42 Figure Serial Loading of Programmable Flag Registers IDT Standard and FWFT Modes 43 Figure Reading of Programmable Flag Registers IDT Standard and FWFT Modes 43 Figure Standard JTAG Timing 44 Figure JTAG Architecture 45 Figure TAP Controller State Diagram 46 Figure Depth Expansion Configuration in IDT Standard Mode 49 Figure Depth Expansion Configuration in FWFT Mode 49 Figure Width Expansion Configuration in IDT Standard Mode and FWFT Mode 50 FEBRUARY 10, 2009 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES The IDT72T6480 sequential flow-control device is a device incorporating a seamless connection to external DDR SDRAM for significant storage capacity supporting high-speed applications. Both read and write ports of the sequential flow-control can operate independently at up to 133MHz. There is a user selectable correction feature that will correct any erroneous single data bit when reading from the SDRAM. The independent read and write ports each has associated read and write clocks, enables, and chip selects. Both ports can operate either synchronously or asynchronously. Other features include bus-matching, programmable status flags with selectable synchronous/asynchronous timing modes, IDT Standard or FWFT mode timing, and JTAG boundary scan functionality. The bus-matching feature will allow the inputs and outputs to be configured to x48, x24, or x12 bus width. There are four default offset values available for the programmable flags PAE/PAF , as well as the option of serially programming the offsets to a specific value. The device package is 19mm x 19mm 324-pin PBGA. It operates at a 2.5V core voltage with selectable 2.5V or 3.3V I/Os. The I/O interface to the SDRAM will be 2.5V SSTL_2 only and not 3.3V tolerant. Both industrial and commercial temperature ranges will be offered. The sequential flow-control device controls individual DDR SDRAM of either 128Mb or 256Mb. The device will support industry standard DDR specification memories note DDR II is not supported , which include vendors such as Samsung, Micron, and Infineon. The data bus connected to the DDR SDRAM can be 16-bit, 32-bit, or 64-bits wide. The sequential flow-control device can independently control up to four separate external memories for a maximum of density of 1Gb 128MB . Depth expansion mode is available for applications that require more than 1Gb of storage memory. FEBRUARY 10, 2009 IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES D[47:0] 48 Input Register Output 48 Register Q[47:0] Input Bus-Matching Logic Output Bus-Matching Logic QP Cache Control Logic Refresh Counter QP Cache 72 x 36 QP Cache 72 x 36 Multi-Clock Arbitration Circuits optional bypass optional bypass Error 72 Detection Check Bit Generator Error 72 Detection Check Bit Generator Correction ORDERING INFORMATION Device Type X Power XX Speed X Package Process / Temperature Range BLANK I 1 Commercial 0°C to +70°C Industrial -40°C to +85°C Plastic Ball Grid Array PBGA, BB324 Commercial Only Clock Cycle Time tCLK Commercial and Industrial Speed in Nanoseconds Low Power 72T6480 2.5V Sequential Flow-Control Device configurable to x12, x24, or x48 6358 drw45 DATASHEET DOCUMENT HISTORY 07/29/2004 pgs. 1, 4, 7-11, 13-25, 27-29, 31-43, 47, 49, and 04/11/2005 pg. 04/15/2005 pg. 10 and 06/28/2005 pgs. 16 and 10/10/2005 pgs. 1, 15 and 02/10/2009 pg. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support 408-360-1533 email:

PDF Datasheet Preview

2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION

For use with 128Mb to 256Mb DDR SDRAM

IDT72T6480
• Product to be used with single or multiple external DDR SDRAM
to provide significant storage capability of up to 1Gb density
• 133MHz operation 7.5ns read/write cycle time
• User selectable input and output port bus-sizing
- x48in to x48out - x48in to x24out - x48in to x12out - x24in to x48out - x24in to x24out - x24in to x12out - x12in to x48out - x12in to x24out - x12in to x12out
• For other bus configurations see IDT72T6360 x9, x18, or x36
• 2.5V-LVTTL or 3.3V-LVTTL configured ports
• Independent and simultaneous read and write access
• User selectable synchronous/asynchronous read and write
port timing
• IDT Standard mode or FWFT mode of operation
• Empty and full flags for monitoring memory status
• Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of four preselected offsets or serially programmed to a specific value
• Selectable synchronous/asynchronous timing modes for

Almost-Empty and Almost-Full flags
• Master Reset clears all data and settings
• Partial Reset clears data, but retains programmable settings
• Depth expandable with multiple devices for densities greater
than 1Gb
• Width expandable with multiple devices for bus widths greater
than 36 bits
• JTAG functionality Boundary Scan
• Available in a 324-pin PBGA, 1mm pitch, 19mm x 19mm
• HIGH performance 0.18µm CMOS technology
• Industrial temperature range -40°C to +85°C is available
• Supports industry standard DDR specifications, including

Samsung, Micron, and Infineon memories

FUNCTIONAL BLOCK DIAGRAM

FWFT FSEL[1:0]

FF/IR PAF EF/OR PAE

Flag Logic
x48, x24, or x12

IDT72T6480 Sequential Flow Control Device

I/O Bus

Reset

Configuration Logic

MRS PRS IOSEL BM[3:0]
x48, x24, or x12

O3u6t-pbiuttsRegister 36-bits

Write Control Logic

Input Register

WEN WCLK/WR

WCS ASYW

DDR SDRAM Control Logic

CK DQS WE CAS RAS Addr

JTAG Control Boundary Scan

MCLK
64 13
36-bits

Read Control Logic
- Read Port Interface 7 - Write Port Interface 7 - Memory Interface 8 - Control and Feature Interface 8 - Power and Ground Signals 10 - Pin Number Location Table 10 Detailed Descriptions 11 Functional Descriptions 22 Signal Descriptions 23 Device Characteristics 27 AC Test Conditions 29 AC Electrical Characteristics 30 JTAG Timing Specifications 45 Depth Expansion Configuration 49 Width Expansion Configuration 50 Ordering Information 51

List of Tables

Table 1 DDR SDRAM Minimum Specifications 11 Table 2 Supported Memory Vendors 11 Table 3 Total Possible External Memory Configurations 12 Table 4 SFC to DDR SDRAM interface Connections 14 Table 5 Total useable memory based on various configurations 18 Table 6 IDT72T6480 Maximum Frequency Based on 166MHz DDR SDRAM 19 Table 7 IDT72T6480 Maximum Frequency Based on 133MHz DDR SDRAM 19 Table 8 MIC[2:0] Configurations 20 Table 9 Memory Configurations Settings 21 Table 10 Device configuration 22 Table Default Programmable Flag Offsets 22 Table Number of Bits Required for Offset Registers 22 Table 13 Bus-Matchings 24 Table 14 MTYPE[1:0] Configurations 25 Table 15 Parameters affected by I/O selection 25

FEBRUARY 10, 2009

IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION

List of Figures

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

Figure Sequential Flow-Control Device Block Diagram 5 Figure 2a. Configuration 1 - Two Chip Solution 13 Figure 2b. Configuration 2 - Two Chip Solution 13 Figure 2c. Configuration 3 - Three Chip Solution 13 Figure 2d. Configuration 4 - Three Chip Solution 13 Figure 2e. Configuration 5 - Three Chip Solution 13 Figure 2f. Configuration 6 - Four Chip Solution 13 Figure 2g. Configuration 7 - Five Chip Solution 13 Figure Memory Interface Connection Single Chip 17 Figure Memory Interface Connection Two Chip 17 Figure 5a. AC Test Load 29 Figure 5b. Lumped Capacitive Load, Typical Derating 29 Figure Master Reset and Initialization 32 Figure Partial Reset 33 Figure Write First Word Cycles - IDT Standard Mode 34 Figure Write First Word Cycles - FWFT Mode 34 Figure Empty Boundary - IDT Standard Mode 35 Figure Empty Boundary - FWFT Mode 35 Figure Full Boundary - IDT Standard Mode 36 Figure Full Boundary - FWFT Mode 36 Figure Output Enable 37 Figure Read Chip Select 37 Figure Write Chip Select 37 Figure Bus-Matching Configuration - x48 In to x24 Out - IDT Standard Mode 38 Figure Bus-Matching Configuration - x48 In to x12 Out - IDT Standard Mode 38 Figure Bus-Matching Configuration - x24 In to x48 Out - IDT Standard Mode 39 Figure Bus-Matching Configuration - x12 In to x48 Out - IDT Standard Mode 39 Figure Synchronous PAE Flag - IDT Standard Mode and FWFT Mode 40 Figure Synchronous PAF Flag - IDT Standard Mode and FWFT Mode 40 Figure Asynchronous Read and PAF Flag - IDT Standard Mode 41 Figure Asynchronous Write and PAE Flag - IDT Standard Mode 41 Figure Asynchronous Write and PAF Flag - IDT Standard Mode 41 Figure Asynchronous Empty Boundary - IDT Standard Mode 42 Figure Asynchronous Full Boundary - IDT Standard Mode 42 Figure Asynchronous Read and PAE Flag - IDT Standard Mode 42 Figure Serial Loading of Programmable Flag Registers IDT Standard and FWFT Modes 43 Figure Reading of Programmable Flag Registers IDT Standard and FWFT Modes 43 Figure Standard JTAG Timing 44 Figure JTAG Architecture 45 Figure TAP Controller State Diagram 46 Figure Depth Expansion Configuration in IDT Standard Mode 49 Figure Depth Expansion Configuration in FWFT Mode 49 Figure Width Expansion Configuration in IDT Standard Mode and FWFT Mode 50

FEBRUARY 10, 2009

IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

The IDT72T6480 sequential flow-control device is a device incorporating a seamless connection to external DDR SDRAM for significant storage capacity supporting high-speed applications. Both read and write ports of the sequential flow-control can operate independently at up to 133MHz. There is a user selectable correction feature that will correct any erroneous single data bit when reading from the SDRAM.

The independent read and write ports each has associated read and write clocks, enables, and chip selects. Both ports can operate either synchronously or asynchronously. Other features include bus-matching, programmable status flags with selectable synchronous/asynchronous timing modes, IDT Standard or FWFT mode timing, and JTAG boundary scan functionality.

The bus-matching feature will allow the inputs and outputs to be configured to x48, x24, or x12 bus width. There are four default offset values available
for the programmable flags PAE/PAF , as well as the option of serially programming the offsets to a specific value.

The device package is 19mm x 19mm 324-pin PBGA. It operates at a 2.5V core voltage with selectable 2.5V or 3.3V I/Os. The I/O interface to the SDRAM will be 2.5V SSTL_2 only and not 3.3V tolerant. Both industrial and commercial temperature ranges will be offered.

The sequential flow-control device controls individual DDR SDRAM of either 128Mb or 256Mb. The device will support industry standard DDR specification memories note DDR II is not supported , which include vendors such as Samsung, Micron, and Infineon. The data bus connected to the DDR SDRAM can be 16-bit, 32-bit, or 64-bits wide. The sequential flow-control device can independently control up to four separate external memories for a maximum of density of 1Gb 128MB . Depth expansion mode is available for applications that require more than 1Gb of storage memory.

FEBRUARY 10, 2009

IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE x12, x24, x48 BIT WIDE CONFIGURATION

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

D[47:0] 48

Input Register

Output 48 Register

Q[47:0]

Input Bus-Matching

Logic

Output Bus-Matching

Logic

QP Cache Control Logic

Refresh Counter

QP Cache 72 x 36

QP Cache 72 x 36

Multi-Clock Arbitration

Circuits
optional bypass
optional bypass

Error 72 Detection

Check Bit Generator

Error 72 Detection

Check Bit Generator

Correction
ORDERING INFORMATION

Device Type

X Power

XX Speed

X Package

Process / Temperature

Range

BLANK I 1

Commercial 0°C to +70°C Industrial -40°C to +85°C

Plastic Ball Grid Array PBGA, BB324

Commercial Only

Clock Cycle Time tCLK

Commercial and Industrial Speed in Nanoseconds

Low Power
72T6480
2.5V Sequential Flow-Control Device configurable to x12, x24, or x48
6358 drw45

DATASHEET DOCUMENT HISTORY
07/29/2004 pgs. 1, 4, 7-11, 13-25, 27-29, 31-43, 47, 49, and 04/11/2005 pg. 04/15/2005 pg. 10 and 06/28/2005 pgs. 16 and 10/10/2005 pgs. 1, 15 and 02/10/2009 pg.

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support 408-360-1533
email:

More datasheets: 84BB-0338-A | 84BB-0350-F | 84BB-0354-A | 84BB-0357-A | 84BB-0361-B | 84BB-0324-C | 84BB-0335-B | 84BB-0307-D | DK-57VTS-LPC3250 | HGTP20N60A4

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Datasheet ID: IDT72T6480L7-5BBG 637358