72T1865L5BBGI8

72T1865L5BBGI8 Datasheet

IDT72T1845, IDT72T1855 IDT72T1865, IDT72T1875 IDT72T1885, IDT72T1895 IDT72T18105, IDT72T18115

Part	Datasheet
72T1865L5BBGI8	72T1865L5BBGI8 (pdf)

Related Parts	Information
72T1865L5BBGI	72T1865L5BBGI
72T1895L5BBI8	72T1895L5BBI8
72T1875L5BBI8	72T1875L5BBI8
72T1865L5BBI8	72T1865L5BBI8
72T1895L6-7BBI	72T1895L6-7BBI
72T1895L4-4BBI	72T1895L4-4BBI

PDF Datasheet Preview
VOLT HIGH-SPEED TeraSync FIFO 18-BIT/9-BIT CONFIGURATIONS 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9, IDT72T1845, IDT72T1855 IDT72T1865, IDT72T1875 IDT72T1885, IDT72T1895 IDT72T18105, IDT72T18115 131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9, 524,288 x 18/1,048,576 x 9 IDT72T18125 FEATURES: • Choose among the following memory organizations IDT72T1845 2,048 x 18/4,096 x 9 IDT72T1855 4,096 x 18/8,192 x 9 IDT72T1865 8,192 x 18/16,384 x 9 IDT72T1875 16,384 x 18/32,768 x 9 IDT72T1885 32,768 x 18/65,536 x 9 IDT72T1895 65,536 x 18/131,072 x 9 IDT72T18105 131,072 x 18/262,144 x 9 IDT72T18115 262,144 x 18/524,288 x 9 IDT72T18125 524,288 x 18/1,048,576 x 9 • Up to 225 MHz Operation of Clocks • User selectable HSTL/LVTTL Input and/or Output • Read Enable & Read Clock Echo outputs aid high speed operation • User selectable Asynchronous read and/or write port timing • 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage • 3.3V Input tolerant • Mark & Retransmit, resets read pointer to user marked position • Write Chip Select WCS input enables/disables Write operations • Read Chip Select RCS synchronous to RCLK • Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets • Program programmable flags by either serial or parallel means • Selectable synchronous/asynchronous timing modes for Almost- Empty and Almost-Full flags • Separate SCLK input for Serial programming of flag offsets • User selectable input and output port bus-sizing - x9 in to x9 out - x9 in to x18 out - x18 in to x9 out - x18 in to x18 out • Big-Endian/Little-Endian user selectable byte representation • Auto power down minimizes standby power consumption • Master Reset clears entire FIFO • Partial Reset clears data, but retains programmable settings • Empty, Full and Half-Full flags signal FIFO status • Select IDT Standard timing using EF and FF flags or First Word Fall Through timing using OR and IR flags • Output enable puts data outputs into high impedance state • JTAG port, provided for Boundary Scan function • Available in 144-pin 13mm x 13mm or 240-pin 19mm x 19mm PlasticBall Grid Array PBGA • Easily expandable in depth and width • Independent Read and Write Clocks permit reading and writing simultaneously • High-performance submicron CMOS technology • Industrial temperature range to +85°C is available • Green parts are available, see ordering information FUNCTIONAL BLOCK DIAGRAM WEN WCLK/WR D0 -Dn x18 or x9 LD SEN SCLK INPUT REGISTER OFFSET REGISTER ASYW BE IP WRITE CONTROL LOGIC WRITE POINTER CONTROL LOGIC RAM ARRAY 2,048 x 18 or 4,096 x 9 4,096 x 18 or 8,192 x 9 8,192 x 18 or 16,384 x 9 16,384 x 18 or 32,768 x 9 32,768 x 18 or 65,536 x 9 65,536 x 18 or 131,072 x 9 131,072 x 18 or 262,144 x 9 262,144 x 18 or 524,288 x 9 524,288 x 18 or 1,048,576 x 9 FLAG LOGIC READ POINTER IW OW MRS PRS BUS CONFIGURATION RESET LOGIC OUTPUT REGISTER READ CONTROL LOGIC TCK TRST TMS TDO JTAG CONTROL BOUNDARY SCAN Vref WHSTL RHSTL SHSTL HSTL I/0 CONTROL OE Q0 -Qn x18 or x9 EREN ERCLK IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. TeraSync FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. FF/IR PAF EF/OR PAE HF FWFT/SI PFM FSEL0 FSEL1 RT MARK ASYR RCLK/RD REN RCS 5909 drw01 FEBRUARY 2009 DSC-5909/19 IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/ 8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN CONFIGURATIONS ORDERING INFORMATION Device Type Power Speed Package Process / Temperature Range BLANK I 1 4-4 5 6-7 10 3 Commercial 0°C to +70°C Industrial -40°C to +85°C Green Plastic Ball Grid Array, PBGA BB144-1 72T1845/55/65/75/85/95 Only Plastic Ball Grid Array, PBGA BB240-1 72T18105/115/125 Only Commercial Only Commercial and Industrial Commercial Only Commercial Only Clock Cycle Time tCLK Speed in Nanoseconds Low Power 72T1845 72T1855 72T1865 72T1875 72T1885 72T1895 72T18105 72T18115 72T18125 2,048 x 18/4,096 x 9 2.5V TeraSync FIFO 4,096 x 18/8,192 x 9 2.5V TeraSync FIFO 8,192 x 18/16,384 x 9 2.5V TeraSync FIFO 16,384 x 18/32,768 x 9 2.5V TeraSync FIFO 32,768 x 18/65,536 x 9 2.5V TeraSync FIFO 65,536 x 18/131,072 x 9 2.5V TeraSync FIFO 131,072 x 18/262,144 x 9 2.5V TeraSync FIFO 262,144 x 18/524,288 x 9 2.5V TeraSync FIFO 524,288 x 18/1,048,576 x 9 2.5V TeraSync FIFO 5909 drw42 NOTES Industrial temperature range product for 5ns speed grade is available as a standard device. All other speed grades are available by special order. Green parts available. For specific speeds and packages contact your sales office. Available for IDT72T18105/72T18115/72T18125 only. DATASHEET DOCUMENT HISTORY 05/30/2001 07/09/2001 pgs. 1, 7, 8, 19, and 10/17/2001 pgs. 1-6, 8, 10, 11, 13-20, 23, 24, 26, 27, 29, 34, 35, 36, 38-43, 11/19/2001 pgs. 1, 9, 12, 38, and 11/29/2001 pgs. 1, 38, and 01/15/2002 03/04/2002 pgs. 9, 10, 17, and 06/05/2002 pgs. 9, 10, and 06/27/2002 02/11/2003 pgs. 8, 9, and 03/03/2003 pgs. 1, 11-13, 29, and 09/02/2003 pgs. 7, 17, and 01/11/2007

PDF Datasheet Preview

VOLT HIGH-SPEED TeraSync FIFO
18-BIT/9-BIT CONFIGURATIONS 2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9, 16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,

IDT72T1845, IDT72T1855 IDT72T1865, IDT72T1875 IDT72T1885, IDT72T1895 IDT72T18105, IDT72T18115
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9, 524,288 x 18/1,048,576 x 9

IDT72T18125

FEATURES:
• Choose among the following memory organizations IDT72T1845 2,048 x 18/4,096 x 9 IDT72T1855 4,096 x 18/8,192 x 9 IDT72T1865 8,192 x 18/16,384 x 9 IDT72T1875 16,384 x 18/32,768 x 9 IDT72T1885 32,768 x 18/65,536 x 9 IDT72T1895 65,536 x 18/131,072 x 9 IDT72T18105 131,072 x 18/262,144 x 9 IDT72T18115 262,144 x 18/524,288 x 9 IDT72T18125 524,288 x 18/1,048,576 x 9
• Up to 225 MHz Operation of Clocks
• User selectable HSTL/LVTTL Input and/or Output
• Read Enable & Read Clock Echo outputs aid high speed operation
• User selectable Asynchronous read and/or write port timing
• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
• 3.3V Input tolerant
• Mark & Retransmit, resets read pointer to user marked position
• Write Chip Select WCS input enables/disables Write operations
• Read Chip Select RCS synchronous to RCLK
• Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets
• Program programmable flags by either serial or parallel means
• Selectable synchronous/asynchronous timing modes for Almost-

Empty and Almost-Full flags
• Separate SCLK input for Serial programming of flag offsets
• User selectable input and output port bus-sizing
- x9 in to x9 out - x9 in to x18 out - x18 in to x9 out - x18 in to x18 out
• Big-Endian/Little-Endian user selectable byte representation
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Select IDT Standard timing using EF and FF flags or First Word Fall Through timing using OR and IR flags
• Output enable puts data outputs into high impedance state
• JTAG port, provided for Boundary Scan function
• Available in 144-pin 13mm x 13mm or 240-pin 19mm x 19mm PlasticBall Grid Array PBGA
• Easily expandable in depth and width
• Independent Read and Write Clocks permit reading and writing simultaneously
• High-performance submicron CMOS technology
• Industrial temperature range to +85°C is available
• Green parts are available, see ordering information

FUNCTIONAL BLOCK DIAGRAM

WEN WCLK/WR

D0 -Dn x18 or x9

LD SEN SCLK

INPUT REGISTER

OFFSET REGISTER

ASYW

BE IP

WRITE CONTROL LOGIC

WRITE POINTER

CONTROL LOGIC

RAM ARRAY 2,048 x 18 or 4,096 x 9 4,096 x 18 or 8,192 x 9 8,192 x 18 or 16,384 x 9 16,384 x 18 or 32,768 x 9 32,768 x 18 or 65,536 x 9 65,536 x 18 or 131,072 x 9 131,072 x 18 or 262,144 x 9 262,144 x 18 or 524,288 x 9 524,288 x 18 or 1,048,576 x 9

FLAG LOGIC

READ POINTER

IW OW

MRS PRS

BUS CONFIGURATION

RESET LOGIC

OUTPUT REGISTER

READ CONTROL

LOGIC

TCK TRST TMS TDO

JTAG CONTROL BOUNDARY SCAN

Vref WHSTL RHSTL SHSTL

HSTL I/0 CONTROL

OE Q0 -Qn x18 or x9

EREN ERCLK

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. TeraSync FIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

FF/IR PAF EF/OR PAE HF FWFT/SI PFM FSEL0 FSEL1

RT MARK ASYR

RCLK/RD REN RCS
5909 drw01

FEBRUARY 2009

DSC-5909/19

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
ORDERING INFORMATION

Device Type Power Speed Package

Process / Temperature

Range

BLANK I 1
4-4 5 6-7 10 3

Commercial 0°C to +70°C Industrial -40°C to +85°C

Green

Plastic Ball Grid Array, PBGA BB144-1 72T1845/55/65/75/85/95 Only Plastic Ball Grid Array, PBGA BB240-1 72T18105/115/125 Only

Commercial Only Commercial and Industrial Commercial Only Commercial Only

Clock Cycle Time tCLK Speed in Nanoseconds

Low Power
72T1845 72T1855 72T1865 72T1875 72T1885 72T1895
72T18105 72T18115 72T18125
2,048 x 18/4,096 x 9 2.5V TeraSync FIFO 4,096 x 18/8,192 x 9 2.5V TeraSync FIFO 8,192 x 18/16,384 x 9 2.5V TeraSync FIFO 16,384 x 18/32,768 x 9 2.5V TeraSync FIFO 32,768 x 18/65,536 x 9 2.5V TeraSync FIFO 65,536 x 18/131,072 x 9 2.5V TeraSync FIFO
131,072 x 18/262,144 x 9 2.5V TeraSync FIFO 262,144 x 18/524,288 x 9 2.5V TeraSync FIFO 524,288 x 18/1,048,576 x 9 2.5V TeraSync FIFO
5909 drw42

NOTES Industrial temperature range product for 5ns speed grade is available as a standard device. All other speed grades are available by special order. Green parts available. For specific speeds and packages contact your sales office. Available for IDT72T18105/72T18115/72T18125 only.

DATASHEET DOCUMENT HISTORY
05/30/2001
07/09/2001
pgs. 1, 7, 8, 19, and
10/17/2001
pgs. 1-6, 8, 10, 11, 13-20, 23, 24, 26, 27, 29, 34, 35, 36, 38-43,
11/19/2001
pgs. 1, 9, 12, 38, and
11/29/2001
pgs. 1, 38, and
01/15/2002
03/04/2002
pgs. 9, 10, 17, and
06/05/2002
pgs. 9, 10, and
06/27/2002
02/11/2003
pgs. 8, 9, and
03/03/2003
pgs. 1, 11-13, 29, and
09/02/2003
pgs. 7, 17, and
01/11/2007

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Datasheet ID: 72T1865L5BBGI8 637353