IDT72P51749L5BB8

IDT72P51749L5BB8 Datasheet

IDT72P51749 IDT72P51759 IDT72P51769

Part	Datasheet
IDT72P51749L5BB8	IDT72P51749L5BB8 (pdf)

Related Parts	Information
IDT72P51769L6BB	IDT72P51769L6BB
IDT72P51769L6BB8	IDT72P51769L6BB8
IDT72P51769L6BBI8	IDT72P51769L6BBI8
IDT72P51769L6BBI	IDT72P51769L6BBI
IDT72P51759L6BBI8	IDT72P51759L6BBI8
IDT72P51769L5BB8	IDT72P51769L5BB8
IDT72P51759L6BB8	IDT72P51759L6BB8
IDT72P51769L5BB	IDT72P51769L5BB
IDT72P51759L6BB	IDT72P51759L6BB
IDT72P51759L5BB8	IDT72P51759L5BB8
IDT72P51759L5BB	IDT72P51759L5BB
IDT72P51749L6BBI8	IDT72P51749L6BBI8
IDT72P51749L6BBI	IDT72P51749L6BBI
IDT72P51749L6BB8	IDT72P51749L6BB8
IDT72P51749L6BB	IDT72P51749L6BB
IDT72P51749L5BB	IDT72P51749L5BB
IDT72P51759L6BBI	IDT72P51759L6BBI

PDF Datasheet Preview
1.8V MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 36 BIT WIDE CONFIGURATION 1,179,648 bits 2,359,296 bits 4,718,592 bits ADVANCE INFORMATION IDT72P51749 IDT72P51759 IDT72P51769 • Choose from among the following memory density options IDT72P51749 Total Available Memory = 1,179,648 bits IDT72P51759 Total Available Memory = 2,359,296 bits IDT72P51769 Total Available Memory = 4,718,592 bits • Configurable from 1 to 128 Queues • Default configuration of 128 or 64 symmetrical queues • Default multi-queue device configurations IDT72P51749 256 x 36 x 128Q IDT72P51759 512 x 36 x 128Q IDT72P51769 1,024 x 36 x 128Q • Default configuration can be augmented via the queue address bus • Number of queues and individual queue sizes may be configured at master reset though serial programming • 200 MHz High speed operation 5ns cycle time • 3.6ns access time • Independent Read and Write access per queue FUNCTIONAL BLOCK DIAGRAM • User Selectable Bus Matching Options: x36 in to x36 out x18 in to x36 out x9 in to x36 out x36in to x18out x18 in to x18 out x9 in to x18 out x36in to x9out x18 in to x9 out x9 in to x9 out • User selectable I/O 1.5V HSTL, 1.8V eHSTL, or 2.5V LVTTL • 100% Bus Utilization, Read and Write on every clock cycle • Selectable First Word Fall Through FWFT or IDT standard mode of operation • Ability to operate on packet or word boundaries • Mark and Re-Write operation • Mark and Re-Read operation • Individual, Active queue flags OR / EF, IR / FF, PAE, PAF, PR • 8 bit parallel flag status on both read and write ports • Direct or polled operation of flag status bus • Expansion of up to 256 queues • JTAG Functionality Boundary Scan • Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm • HIGH Performance submicron CMOS technology • Industrial temperature range -40°C to +85°C is available MULTI-QUEUE FLOW-CONTROL DEVICE WADEN FSTR WRADD WEN 8 WCLK WCS x36, 18 or x9 DATA IN FF/IR PAF PAFn WRITE CONTROL Q127 Q126 Q125 WRITE FLAGS IDT and the IDT logo are trademarks of Integrated Device Technology, Inc COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. READ FLAGS Serial Programming 23 Default Programming 23 Parallel Programming 23 Queue description 25 Configuration of the IDT Multi-queue flow-control device 25 Standard mode operation 26 Read Queue Selection and Read Operation 27 Switching Queues on the Write Port 29 Switching Queues on the Read Port 31 Flag description 42 PAFn Flag Bus Operation 42 Full Flag Operation 42 Empty or Output Ready Flag Operation EF/OR 42 Almost Full Flag 43 Almost Empty Flag 43 Packet Ready Flag 47 Packet Mode Demarcation bits 49 JTAG Interface 82 JTAG AC electrical characteristics 86 Ordering Information 87 List of Tables Table 1 Device programming mode comparison 22 Table 2 Setting the queue programming mode during master reset 22 Table 3 Mode Configuration 25 Table 4 Write Address Bus, WRADD[7:0] 26 Table 5 Read Address Bus, RDADD[7:0] 27 Table 6 Write Queue Switch Operation 30 Table 7 Read Queue Switch Operation 32 Table 8 Same Queue Switch 32 Table 9 Flag operation boundaries and Timing 45 Table 10 Packet Mode Valid Byte for x36 bit word configuration 48 Table 11 Bus-Matching Set-Up 52 SEPTEMBER 27, 2004 IDT72P51749/72P51759/72P51769 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 36 BIT WIDE CONFIGURATION 1,179,648, 2,359,296, and 4,718,592 bits List of Figures COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Figure Multi-Queue Flow-Control Device Block Diagram 6 Figure 2a. AC Test Load 19 Figure 2b. Lumped Capacitive Load, Typical Derating 19 Figure Reference Signals 22 Figure Device Programming Hierarchy 24 Figure IDT Standard mode illustrated Read Port 25 Figure First Word Fall Through FWFT mode illustrated Read Port 25 Figure Write Port Switching Queues Signal Sequence 29 Figure Switching Queues Bus Efficiency 29 Figure Simultaneous Queue Switching 30 Figure Read Port Switching Queues Signal Sequence 31 Figure Switching Queues Bus Efficiency 31 Figure Simultaneous Queue Switching 32 Figure MARK and Re-Write Sequence 33 Figure MARK and Re-Read Sequence 33 Figure MARKing a Queue in Packet Mode - Write Queue MARK 34 Figure MARKing a Queue in Packet Mode - Read Queue MARK 34 Figure UN-MARKing a Queue in Packet Mode - Write Queue UN-MARK 35 Figure UN-MARKing a Queue in Packet Mode - Read Queue UN-MARK 35 Figure MARKing a Queue in FIFO Mode - Write Queue MARK 37 Figure MARKing a Queue in FIFO Mode - Read Queue MARK 37 Figure UN-MARKing a Queue in FIFO Mode - Write Queue UN-MARK 38 Figure UN-MARKing a Queue in FIFO Mode - Read Queue UN-MARK 38 Figure Leaving a MARK active on the Write Port 39 Figure Leaving a MARK active on the Read Port 39 Figure Inactivating a MARK on the Write Port Active 40 Figure Inactivating a MARK on the Read Port Active 40 Figure 36bit to 36bit word configuration 49 Figure 36bit to 18bit word configuration 49 Figure 36bit to 9bit word configuration 49 Figure 18bit to 36bit word configuration 50 Figure 18bit to 18bit word configuration 50 Figure 18bit to 9bit word configuration 50 Figure 9bit to 36bit word configuration 51 Figure 9bit to 18bit word configuration 51 Figure 9bit to 9bit word configuration 51 Figure Bus-Matching Byte Arrangement 53 Figure Master Reset 54 Figure Default Programming 55 Figure Parallel Programming 56 Figure Queue Programming via Write Address Bus 57 Figure Queue Programming via Read Address Bus 57 Figure Serial Port Connection for Serial Programming 57 Figure Serial Programming 2 Device Expansion 58 Figure Write Queue Select, Write Operation and Full Flag Operation 59 Figure Write Queue Select, Mark and Rewrite 60 Figure Write Operations in First Word Fall Through mode 61 Figure Full Flag Timing in Expansion Configuration 62 Figure Read Queue Select, Read Operation IDT mode 63 Figure Read Queue Select, Read Operation FWFT mode 64 Figure Read Queue Select, Mark and Reread IDT mode 65 Figure Output Ready Flag Timing In FWFT Mode 66 Figure Read Queue Selection with Read Operations IDT mode 67 Figure Read Queue Select, Read Operation and OE Timing 68 Figure Writing in Packet Mode during a Queue change 69 SEPTEMBER 27, 2004 IDT72P51749/72P51759/72P51769 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 36 BIT WIDE CONFIGURATION 1,179,648, 2,359,296, and 4,718,592 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES List of Figures Continued Figure Reading in Packet Mode during a Queue change 70 Figure Writing Demarcation Bits Packet Mode 71 Figure Data Output Receive Packet Mode of Operation 72 Figure Almost Full Flag Timing and Queue Switch 73 Figure Almost Full Flag Timing 73 Figure Almost Empty Flag Timing and Queue Switch FWFT mode 74 Figure Almost Empty Flag Timing 74 Figure PAEn/PRn - Direct Mode - Status Word Selection 75 Figure PAFn - Direct Mode - Status Word Selection 75 Figure PAEn - Direct Mode, Flag Operation 76 Figure PAFn - Direct Mode, Flag Operation 77 Figure PAFn Bus - Polled Mode 78 Figure Expansion using ID codes 79 Figure Expansion using WCS/RCS 80 Figure Expansion Connection Read Chip Select RCS 81 Figure Expansion Connection Write Chip Select WCS 81 Figure Boundary Scan Architecture 82 Figure TAP Controller State Diagram 83 Figure Standard JTAG Timing 86 SEPTEMBER 27, 2004 IDT72P51749/72P51759/72P51769 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 36 BIT WIDE CONFIGURATION 1,179,648, 2,359,296, and 4,718,592 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES The IDT72P51749/72P51759/72P51769 multi-queue flow-control devices are single chips with up to 128 discrete configurable FIFO queues. All queues within the device have a common data input bus, write port and a common data output bus, read port . Data written into the write port is directed to a specific queue via an internal de-multiplex operation, addressed by the write address bus WRADD . Data read from the read port is accessed from a specific queue via an internal multiplex operation, addressed by the read address bus RDADD . Data writes and reads can be performed at high speeds up to 200MHz, with access times of 3.6ns. Data write and read operations are totally independent of each other, a queue maybe selected on the write port and a different queue on the read port or both ports may select the same queue simultaneously. The device provides Full flag and Empty flag status for the queue selected for write and read operations respectively. Also a Programmable Almost Full and Programmable Almost Empty flag for each queue is provided. Two 8 bit programmable flag busses are available, providing status of queues not selected for write or read operations. When 8 or less queues are configured in the device these flag busses provide an individual flag per queue, when more than 8 queues are used, either a Polled or Direct mode bus operation provides the flag busses with all queues status. Bus Matching is available on this device, either port can be 9 bits, 18 bits or 36 bits wide. When Bus Matching is used the device ensures the logical transfer of data throughput in a Little Endian manner. A packet mode of operation is also provided. Packet mode provides a packet ready flag output PR indicating when at least one or more packets of data within a queue is available for reading. The Packet Ready indicator is generated upon detection of the start and end of packet demarcation bits. The multi-queue device then provides the user with an internally generated packet ready status per queue. The user has full flexibility configuring queues within the device, being able to program the total number of queues between 1 and 128, the individual queue depths being independent of each other. The programmable flag positions are also user programmable. All programming is done via a dedicated serial port. If the user does not wish to program the multi-queue device, a default option is available that configures the device in a predetermined manner. A Master Reset must be provided to the device. A Master Reset latches in configuration/setup pins and must be performed before further programming of the device can take place. On the rising edge of master reset the device operating mode is set, the device programming mode serial, parallel or default is set and the expansion configuration device type master or slave is set. The multi-queue flow-control device has the capability of operating its I/O in either 2.5V LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of I/O is selected via the IOSEL input. The core supply voltage VDD to the multi-queue is 1.8V, however the output levels can be set independently via a separate supply, VDDQ. A JTAG test port is provided, here the multi-queue flow-control device has a fully functional Boundary Scan feature, compliant with IEEE Standard Test Access Port and Boundary Scan Architecture. See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an outline of the functional blocks within the device. SEPTEMBER 27, 2004 IDT72P51749/72P51759/72P51769 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 36 BIT WIDE CONFIGURATION 1,179,648, 2,359,296, and 4,718,592 bits COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 8 WRADD WADEN WCLK WEN WCS ORDERING INFORMATION IDT Device Type X Power XX Speed X Package Process / Temperature Range BLANK I 1 Commercial 0°C to +70°C Industrial -40°C to +85°C Plastic Ball Grid Array PBGA, BB256-1 Commercial Only Clock Cycle Time tCLK Commercial and Industrial Speed in Nanoseconds Low Power 72P51749 1,179,648 bits 1.8V Multi-Queue Flow-Control Device 72P51759 2,359,296 bits 1.8V Multi-Queue Flow-Control Device 72P51769 4,718,592 bits 1.8V Multi-Queue Flow-Control Device NOTE: 6714 drw79 Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES 800-345-7015 or 408-727-6116 fax 408-492-8674 for Tech Support 408-330-1533 email:

PDF Datasheet Preview

1.8V MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 36 BIT WIDE CONFIGURATION 1,179,648 bits 2,359,296 bits 4,718,592 bits

ADVANCE INFORMATION

IDT72P51749 IDT72P51759 IDT72P51769
• Choose from among the following memory density options IDT72P51749 Total Available Memory = 1,179,648 bits IDT72P51759 Total Available Memory = 2,359,296 bits IDT72P51769 Total Available Memory = 4,718,592 bits
• Configurable from 1 to 128 Queues
• Default configuration of 128 or 64 symmetrical queues
• Default multi-queue device configurations

IDT72P51749 256 x 36 x 128Q IDT72P51759 512 x 36 x 128Q IDT72P51769 1,024 x 36 x 128Q
• Default configuration can be augmented via the queue address bus
• Number of queues and individual queue sizes may be configured at master reset though serial programming
• 200 MHz High speed operation 5ns cycle time
• 3.6ns access time
• Independent Read and Write access per queue

FUNCTIONAL BLOCK DIAGRAM
• User Selectable Bus Matching Options:
x36 in to x36 out x18 in to x36 out
x9 in to x36 out
x36in to x18out
x18 in to x18 out
x9 in to x18 out
x36in to x9out
x18 in to x9 out
x9 in to x9 out
• User selectable I/O 1.5V HSTL, 1.8V eHSTL, or 2.5V LVTTL
• 100% Bus Utilization, Read and Write on every clock cycle
• Selectable First Word Fall Through FWFT or IDT standard
mode of operation
• Ability to operate on packet or word boundaries
• Mark and Re-Write operation
• Mark and Re-Read operation
• Individual, Active queue flags OR / EF, IR / FF, PAE, PAF, PR
• 8 bit parallel flag status on both read and write ports
• Direct or polled operation of flag status bus
• Expansion of up to 256 queues
• JTAG Functionality Boundary Scan
• Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
• HIGH Performance submicron CMOS technology
• Industrial temperature range -40°C to +85°C is available

MULTI-QUEUE FLOW-CONTROL DEVICE

WADEN FSTR WRADD WEN 8 WCLK WCS
x36, 18 or x9 DATA IN

FF/IR PAF PAFn

WRITE CONTROL

Q127 Q126 Q125

WRITE FLAGS

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1

Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

READ FLAGS
Serial Programming 23 Default Programming 23 Parallel Programming 23 Queue description 25 Configuration of the IDT Multi-queue flow-control device 25 Standard mode operation 26 Read Queue Selection and Read Operation 27 Switching Queues on the Write Port 29 Switching Queues on the Read Port 31 Flag description 42 PAFn Flag Bus Operation 42 Full Flag Operation 42 Empty or Output Ready Flag Operation EF/OR 42 Almost Full Flag 43 Almost Empty Flag 43 Packet Ready Flag 47 Packet Mode Demarcation bits 49 JTAG Interface 82 JTAG AC electrical characteristics 86 Ordering Information 87

List of Tables

Table 1 Device programming mode comparison 22 Table 2 Setting the queue programming mode during master reset 22 Table 3 Mode Configuration 25 Table 4 Write Address Bus, WRADD[7:0] 26 Table 5 Read Address Bus, RDADD[7:0] 27 Table 6 Write Queue Switch Operation 30 Table 7 Read Queue Switch Operation 32 Table 8 Same Queue Switch 32 Table 9 Flag operation boundaries and Timing 45 Table 10 Packet Mode Valid Byte for x36 bit word configuration 48 Table 11 Bus-Matching Set-Up 52

SEPTEMBER 27, 2004

IDT72P51749/72P51759/72P51769 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 36 BIT WIDE CONFIGURATION 1,179,648, 2,359,296, and 4,718,592 bits

List of Figures

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

Figure Multi-Queue Flow-Control Device Block Diagram 6 Figure 2a. AC Test Load 19 Figure 2b. Lumped Capacitive Load, Typical Derating 19 Figure Reference Signals 22 Figure Device Programming Hierarchy 24 Figure IDT Standard mode illustrated Read Port 25 Figure First Word Fall Through FWFT mode illustrated Read Port 25 Figure Write Port Switching Queues Signal Sequence 29 Figure Switching Queues Bus Efficiency 29 Figure Simultaneous Queue Switching 30 Figure Read Port Switching Queues Signal Sequence 31 Figure Switching Queues Bus Efficiency 31 Figure Simultaneous Queue Switching 32 Figure MARK and Re-Write Sequence 33 Figure MARK and Re-Read Sequence 33 Figure MARKing a Queue in Packet Mode - Write Queue MARK 34 Figure MARKing a Queue in Packet Mode - Read Queue MARK 34 Figure UN-MARKing a Queue in Packet Mode - Write Queue UN-MARK 35 Figure UN-MARKing a Queue in Packet Mode - Read Queue UN-MARK 35 Figure MARKing a Queue in FIFO Mode - Write Queue MARK 37 Figure MARKing a Queue in FIFO Mode - Read Queue MARK 37 Figure UN-MARKing a Queue in FIFO Mode - Write Queue UN-MARK 38 Figure UN-MARKing a Queue in FIFO Mode - Read Queue UN-MARK 38 Figure Leaving a MARK active on the Write Port 39 Figure Leaving a MARK active on the Read Port 39 Figure Inactivating a MARK on the Write Port Active 40 Figure Inactivating a MARK on the Read Port Active 40 Figure 36bit to 36bit word configuration 49 Figure 36bit to 18bit word configuration 49 Figure 36bit to 9bit word configuration 49 Figure 18bit to 36bit word configuration 50 Figure 18bit to 18bit word configuration 50 Figure 18bit to 9bit word configuration 50 Figure 9bit to 36bit word configuration 51 Figure 9bit to 18bit word configuration 51 Figure 9bit to 9bit word configuration 51 Figure Bus-Matching Byte Arrangement 53 Figure Master Reset 54 Figure Default Programming 55 Figure Parallel Programming 56 Figure Queue Programming via Write Address Bus 57 Figure Queue Programming via Read Address Bus 57 Figure Serial Port Connection for Serial Programming 57 Figure Serial Programming 2 Device Expansion 58 Figure Write Queue Select, Write Operation and Full Flag Operation 59 Figure Write Queue Select, Mark and Rewrite 60 Figure Write Operations in First Word Fall Through mode 61 Figure Full Flag Timing in Expansion Configuration 62 Figure Read Queue Select, Read Operation IDT mode 63 Figure Read Queue Select, Read Operation FWFT mode 64 Figure Read Queue Select, Mark and Reread IDT mode 65 Figure Output Ready Flag Timing In FWFT Mode 66 Figure Read Queue Selection with Read Operations IDT mode 67 Figure Read Queue Select, Read Operation and OE Timing 68 Figure Writing in Packet Mode during a Queue change 69

SEPTEMBER 27, 2004

IDT72P51749/72P51759/72P51769 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 36 BIT WIDE CONFIGURATION 1,179,648, 2,359,296, and 4,718,592 bits

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

List of Figures Continued

Figure Reading in Packet Mode during a Queue change 70

Figure Writing Demarcation Bits Packet Mode 71

Figure Data Output Receive Packet Mode of Operation 72

Figure Almost Full Flag Timing and Queue Switch 73

Figure Almost Full Flag Timing 73

Figure Almost Empty Flag Timing and Queue Switch FWFT mode 74

Figure Almost Empty Flag Timing 74 Figure PAEn/PRn - Direct Mode - Status Word Selection 75 Figure PAFn - Direct Mode - Status Word Selection 75 Figure PAEn - Direct Mode, Flag Operation 76 Figure PAFn - Direct Mode, Flag Operation 77 Figure PAFn Bus - Polled Mode 78

Figure Expansion using ID codes 79 Figure Expansion using WCS/RCS 80 Figure Expansion Connection Read Chip Select RCS 81 Figure Expansion Connection Write Chip Select WCS 81

Figure Boundary Scan Architecture 82

Figure TAP Controller State Diagram 83

Figure Standard JTAG Timing 86

SEPTEMBER 27, 2004

IDT72P51749/72P51759/72P51769 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 36 BIT WIDE CONFIGURATION 1,179,648, 2,359,296, and 4,718,592 bits

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

The IDT72P51749/72P51759/72P51769 multi-queue flow-control devices are single chips with up to 128 discrete configurable FIFO queues. All queues within the device have a common data input bus, write port and a common data output bus, read port . Data written into the write port is directed to a specific queue via an internal de-multiplex operation, addressed by the write address bus WRADD . Data read from the read port is accessed from a specific queue via an internal multiplex operation, addressed by the read address bus RDADD . Data writes and reads can be performed at high speeds up to 200MHz, with access times of 3.6ns. Data write and read operations are totally independent of each other, a queue maybe selected on the write port and a different queue on the read port or both ports may select the same queue simultaneously.

The device provides Full flag and Empty flag status for the queue selected for write and read operations respectively. Also a Programmable Almost Full and Programmable Almost Empty flag for each queue is provided. Two 8 bit programmable flag busses are available, providing status of queues not selected for write or read operations. When 8 or less queues are configured in the device these flag busses provide an individual flag per queue, when more than 8 queues are used, either a Polled or Direct mode bus operation provides the flag busses with all queues status.

Bus Matching is available on this device, either port can be 9 bits, 18 bits or 36 bits wide. When Bus Matching is used the device ensures the logical transfer of data throughput in a Little Endian manner.

A packet mode of operation is also provided. Packet mode provides a packet ready flag output PR indicating when at least one or more packets of data
within a queue is available for reading. The Packet Ready indicator is generated upon detection of the start and end of packet demarcation bits. The multi-queue device then provides the user with an internally generated packet ready status per queue.

The user has full flexibility configuring queues within the device, being able to program the total number of queues between 1 and 128, the individual queue depths being independent of each other. The programmable flag positions are also user programmable. All programming is done via a dedicated serial port. If the user does not wish to program the multi-queue device, a default option is available that configures the device in a predetermined manner.

A Master Reset must be provided to the device. A Master Reset latches in configuration/setup pins and must be performed before further programming of the device can take place. On the rising edge of master reset the device operating mode is set, the device programming mode serial, parallel or default is set and the expansion configuration device type master or slave is set.

The multi-queue flow-control device has the capability of operating its I/O in either 2.5V LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of I/O is selected via the IOSEL input. The core supply voltage VDD to the multi-queue is 1.8V, however the output levels can be set independently via a separate supply, VDDQ.

A JTAG test port is provided, here the multi-queue flow-control device has a fully functional Boundary Scan feature, compliant with IEEE Standard Test Access Port and Boundary Scan Architecture.

See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an outline of the functional blocks within the device.

SEPTEMBER 27, 2004

IDT72P51749/72P51759/72P51769 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES 128 QUEUES 36 BIT WIDE CONFIGURATION 1,179,648, 2,359,296, and 4,718,592 bits

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
8 WRADD WADEN

WCLK WEN WCS
ORDERING INFORMATION

IDT Device Type

X Power

XX Speed

X Package

Process / Temperature

Range

BLANK I 1

Commercial 0°C to +70°C Industrial -40°C to +85°C

Plastic Ball Grid Array PBGA, BB256-1

Commercial Only

Clock Cycle Time tCLK

Commercial and Industrial Speed in Nanoseconds

Low Power
72P51749 1,179,648 bits 1.8V Multi-Queue Flow-Control Device 72P51759 2,359,296 bits 1.8V Multi-Queue Flow-Control Device
72P51769 4,718,592 bits 1.8V Multi-Queue Flow-Control Device

NOTE:
6714 drw79

Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order.

CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES 800-345-7015 or 408-727-6116 fax 408-492-8674
for Tech Support 408-330-1533
email:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT72P51749L5BB8 Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT72P51749L5BB8 637351