IDT71V65602S150PFGI

IDT71V65602S150PFGI Datasheet

IDT71V65602/Z IDT71V65802/Z

Part	Datasheet
IDT71V65602S150PFGI	IDT71V65602S150PFGI (pdf)

Related Parts	Information
IDT71V65602S133BG8	IDT71V65602S133BG8
IDT71V65602S150PFG8	IDT71V65602S150PFG8
IDT71V65602S150PFG	IDT71V65602S150PFG
IDT71V65602S150PF8	IDT71V65602S150PF8
IDT71V65602S150PF	IDT71V65602S150PF
IDT71V65602S150BQ	IDT71V65602S150BQ
IDT71V65602S150BG8	IDT71V65602S150BG8
IDT71V65602S150BG	IDT71V65602S150BG
IDT71V65602S133PFI	IDT71V65602S133PFI
IDT71V65602S133BQ	IDT71V65602S133BQ
IDT71V65602S133BQ8	IDT71V65602S133BQ8
IDT71V65602S133BG	IDT71V65602S133BG
IDT71V65602S133PF	IDT71V65602S133PF
IDT71V65602S150PFI8	IDT71V65602S150PFI8
IDT71V65602S133PF8	IDT71V65602S133PF8
IDT71V65602S133PFG	IDT71V65602S133PFG
IDT71V65602S133PFG8	IDT71V65602S133PFG8
IDT71V65602S133PFI8	IDT71V65602S133PFI8
IDT71V65802S150BGG8	IDT71V65802S150BGG8
IDT71V65802S133PF	IDT71V65802S133PF
IDT71V65802S133PF8	IDT71V65802S133PF8
IDT71V65802S133PFG	IDT71V65802S133PFG
IDT71V65802S133PFG8	IDT71V65802S133PFG8
IDT71V65802S150BG	IDT71V65802S150BG
IDT71V65602S150PFGI8	IDT71V65602S150PFGI8
IDT71V65802S150BGG	IDT71V65802S150BGG
IDT71V65802S133BQ8	IDT71V65802S133BQ8
IDT71V65802S150BQ	IDT71V65802S150BQ
IDT71V65802S150BQ8	IDT71V65802S150BQ8
IDT71V65802S150PF	IDT71V65802S150PF
IDT71V65802S150PF8	IDT71V65802S150PF8
IDT71V65802ZS133BG	IDT71V65802ZS133BG
IDT71V65802ZS133BG8	IDT71V65802ZS133BG8
IDT71V65802S150BG8	IDT71V65802S150BG8
IDT71V65802S100PF8	IDT71V65802S100PF8
IDT71V65602S100BQ	IDT71V65602S100BQ
IDT71V65602ZS133BG	IDT71V65602ZS133BG
IDT71V65602ZS133BG8	IDT71V65602ZS133BG8
IDT71V65802S100BG	IDT71V65802S100BG
IDT71V65802S100BG8	IDT71V65802S100BG8
IDT71V65802S100BQ	IDT71V65802S100BQ
IDT71V65802S133BQI8	IDT71V65802S133BQI8
IDT71V65802S100PF	IDT71V65802S100PF
IDT71V65802S133BQI	IDT71V65802S133BQI
IDT71V65802S100PFG	IDT71V65802S100PFG
IDT71V65802S100PFG8	IDT71V65802S100PFG8
IDT71V65802S133BG	IDT71V65802S133BG
IDT71V65802S133BG8	IDT71V65802S133BG8
IDT71V65802S133BQ	IDT71V65802S133BQ
IDT71V65602S150PFI	IDT71V65602S150PFI
IDT71V65802S100BQ8	IDT71V65802S100BQ8
IDT71V65602S100BG8	IDT71V65602S100BG8
IDT71V65602S100PFGI8	IDT71V65602S100PFGI8
IDT71V65602S100BG	IDT71V65602S100BG
IDT71V65602S100PF	IDT71V65602S100PF
IDT71V65602S100BQ8	IDT71V65602S100BQ8
IDT71V65602S100PF8	IDT71V65602S100PF8
IDT71V65602S100PFG	IDT71V65602S100PFG
IDT71V65602S100PFG8	IDT71V65602S100PFG8
IDT71V65602S100PFGI	IDT71V65602S100PFGI

PDF Datasheet Preview
256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs IDT71V65602/Z IDT71V65802/Z 256K x 36, 512K x 18 memory configurations Supports high performance system speed - 150MHz 3.8ns Clock-to-Data Access ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R/W READ/WRITE control pin Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications 4-word burst capability interleaved or linear Individual byte write BW1 - BW4 control May tie active Three chip enables for simple depth expansion 3.3V power supply ±5% 2.5V I/O Supply VDDQ Power down controlled by ZZ input Packaged in a JEDEC standard 100-pin plastic thin quad and flatpack TQFP , 119 ball grid array BGA and 165 fine pitch ball grid array fBGA The IDT71V65602/5802 are 3.3V high-speed 9,437,184-bit 9 Megabit synchronous SRAMs. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. The IDT71V65602/5802 contain data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable CEN pin allows operation of the IDT71V65602/5802 to be suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous values. There are three chip enable pins CE1, CE2, CE2 that allow the user to deselect the device when desired. If any one of these three are not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers reads or writes will be completed. The data bus will tri-state two cycles after chip is deselected or a write is initiated. The IDT71V65602/5802 have an on-chip burst counter. In the burst mode, the IDT71V65602/5802 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address ADV/ LD = LOW or increment the internal burst counter ADV/LD = HIGH . The IDT71V65602/5802 SRAM utilize IDT's latest high-performance CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm 100pin thin plastic quad flatpack TQFP as well as a 119 ball grid array BGA and a 165 fine pitch ball grid array fBGA . Pin Description Summary A0-A18 Address Inputs CE1, CE2, CE2 Chip Enables Output Enable Read/Write Signal Clock Enable BW1, BW2, BW3, BW4 Individual Byte Write Selects Clock ADV/LD Advance burst address / Load new address Linear / Interleaved Burst Order Sleep Mode I/O0-I/O31, I/OP1-I/OP4 Data Input / Output VDD, VDDQ Core Power, I/O Power Ground Input I/O Supply Synchronous Asynchronous Synchronous N/A Synchronous Static Asynchronous Synchronous Static 5303 tbl 01 ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc. Ordering Information XXXX Z S Device Type Power XX Speed Package Process/ Temperature Range Blank I PF BG BQ Commercial 0° C to +70° C Industrial -40° C to +85° C 100 pin Plastic Thin Quad Flatpack, 100 pin 119 Ball Grid Array BGA 165 Fine Pitch Ball Grid Array fBGA Clock Frequency in Megahertz Blank First generation or current die step Current generation die step optional IDT71V65602 256Kx36 Pipelined ZBT SRAM IDT71V65802 512Kx18 Pipelined ZBT SRAM 5303 drw 12 IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Datasheet Document History 12/31/99 03/04/00 04/20/00 05/16/00 07/28/00 11/04/00 12/04/02 12/19/02 10/15/04 02/21/07 02/20/09 Created new datasheet from obsolete devices IDT71V656 and IDT71V658 Pg.1,14,15 Removed 166MHz speed grade offering Added 150MHz speed grade offering Pg. 5,6 Add JTAG test pins to TQFP pin configuration removed footnote Add clarification note to Recommended Operating Temperature and Absolute Max Ratings tables Pg. 7 Add note to BGA Pin configuration corrected typo in pinout Pg. 21 Insert TQFP Package Diagram Outline Add new package offering, 13 x 15mm 165fBGA Pg. 23 Correct error in the 119 BGA Package Diagram Outline Pg. 5-8 Remove JTAG pins from TQFP, BG119 and BQ165 pinouts, refer to IDT71V656xx and IDT71V658xx device errata Pg. 7,8 Correct error in pinout, B2 on BG119 and B1 on BQ165 pinout Pg. 23 Update BG119 Package Diagram Dimensions Pg. 15 Add Izz parameter to DC Electrical Characteristics Added Z generation die step to data sheet ordering information. Pg.25 Removed "IDT" from orderable parts number. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Rd San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 The IDT logo is a registered trademark of Integrated Device Technology, Inc. for Tech Support 800-345-7015 or 408/284-4555

PDF Datasheet Preview

256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs

IDT71V65602/Z IDT71V65802/Z
256K x 36, 512K x 18 memory configurations Supports high performance system speed - 150MHz
3.8ns Clock-to-Data Access ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the
need to control OE Single R/W READ/WRITE control pin Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications 4-word burst capability interleaved or linear Individual byte write BW1 - BW4 control May tie active Three chip enables for simple depth expansion 3.3V power supply ±5% 2.5V I/O Supply VDDQ Power down controlled by ZZ input Packaged in a JEDEC standard 100-pin plastic thin quad and
flatpack TQFP , 119 ball grid array BGA and 165 fine pitch ball grid array fBGA

The IDT71V65602/5802 are 3.3V high-speed 9,437,184-bit 9 Megabit synchronous SRAMs. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround.

Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write.

The IDT71V65602/5802 contain data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time.

A Clock Enable CEN pin allows operation of the IDT71V65602/5802 to be suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous values.

There are three chip enable pins CE1, CE2, CE2 that allow the user to deselect the device when desired. If any one of these three are not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers reads or writes will be completed. The data bus will tri-state two cycles after chip is deselected or a write is initiated.

The IDT71V65602/5802 have an on-chip burst counter. In the burst mode, the IDT71V65602/5802 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address ADV/ LD = LOW or increment the internal burst counter ADV/LD = HIGH .

The IDT71V65602/5802 SRAM utilize IDT's latest high-performance CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm 100pin thin plastic quad flatpack TQFP as well as a 119 ball grid array BGA and a 165 fine pitch ball grid array fBGA .

Pin Description Summary

A0-A18

Address Inputs

CE1, CE2, CE2

Chip Enables

Output Enable

Read/Write Signal

Clock Enable

BW1, BW2, BW3, BW4

Individual Byte Write Selects

Clock

ADV/LD

Advance burst address / Load new address

Linear / Interleaved Burst Order

Sleep Mode

I/O0-I/O31, I/OP1-I/OP4

Data Input / Output

VDD, VDDQ

Core Power, I/O Power

Ground

Input I/O Supply

Synchronous Asynchronous Synchronous

N/A Synchronous

Static Asynchronous Synchronous

Static
5303 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
Ordering Information

XXXX Z S

Device Type

Power

XX Speed

Package

Process/ Temperature Range

Blank I

PF BG BQ

Commercial 0° C to +70° C Industrial -40° C to +85° C
100 pin Plastic Thin Quad Flatpack, 100 pin 119 Ball Grid Array BGA 165 Fine Pitch Ball Grid Array fBGA

Clock Frequency in Megahertz

Blank First generation or current die step

Current generation die step optional

IDT71V65602 256Kx36 Pipelined ZBT SRAM IDT71V65802 512Kx18 Pipelined ZBT SRAM
5303 drw 12

IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with

ZBT Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Datasheet Document History
12/31/99 03/04/00 04/20/00
05/16/00 07/28/00
11/04/00 12/04/02
12/19/02
10/15/04
02/21/07 02/20/09

Created new datasheet from obsolete devices IDT71V656 and IDT71V658

Pg.1,14,15 Removed 166MHz speed grade offering Added 150MHz speed grade offering

Pg. 5,6 Add JTAG test pins to TQFP pin configuration removed footnote

Add clarification note to Recommended Operating Temperature and Absolute Max Ratings tables

Pg. 7

Add note to BGA Pin configuration corrected typo in pinout

Pg. 21 Insert TQFP Package Diagram Outline

Add new package offering, 13 x 15mm 165fBGA

Pg. 23

Correct error in the 119 BGA Package Diagram Outline

Pg. 5-8 Remove JTAG pins from TQFP, BG119 and BQ165 pinouts, refer to IDT71V656xx and IDT71V658xx
device errata

Pg. 7,8 Correct error in pinout, B2 on BG119 and B1 on BQ165 pinout

Pg. 23 Update BG119 Package Diagram Dimensions

Pg. 15 Add Izz parameter to DC Electrical Characteristics
Added Z generation die step to data sheet ordering information.

Pg.25 Removed "IDT" from orderable parts number.

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Rd San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
for Tech Support 800-345-7015 or 408/284-4555

More datasheets: 6N139 | 6N138M | 6N138S-TA1 | 6N139M | 6N138S | 6N139S | 6N138 | BSO4420 | BSO4420T | IDT71V65602S133BG8

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Datasheet ID: IDT71V65602S150PFGI 637342