IDT71V546S133PF8

IDT71V546S133PF8 Datasheet

128K x 36, 3.3V Synchronous IDT71V546S/XS SRAM with ZBT Feature, Burst Counter and Pipelined Outputs

Part	Datasheet
IDT71V546S133PF8	IDT71V546S133PF8 (pdf)

Related Parts	Information
IDT71V546S100PF	IDT71V546S100PF
IDT71V546S100PF8	IDT71V546S100PF8
IDT71V546S100PFI	IDT71V546S100PFI
IDT71V546S133PF	IDT71V546S133PF
IDT71V546S133PFI	IDT71V546S133PFI
IDT71V546S133PFI8	IDT71V546S133PFI8
IDT71V546XS133PF	IDT71V546XS133PF
IDT71V546XS133PF8	IDT71V546XS133PF8
IDT71V546XS133PFI8	IDT71V546XS133PFI8
IDT71V546XS133PFI	IDT71V546XS133PFI
IDT71V546S100PFI8	IDT71V546S100PFI8

PDF Datasheet Preview
128K x 36, 3.3V Synchronous IDT71V546S/XS SRAM with ZBT Feature, Burst Counter and Pipelined Outputs 128K x 36 memory configuration, pipelined outputs Supports high performance system speed - 133 MHz ns Clock-to-Data Access ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized registered outputs eliminate the need to control OE Single R/W READ/WRITE control pin Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications 4-word burst capability interleaved or linear Individual byte write BW1 - BW4 control May tie active Three chip enables for simple depth expansion Single 3.3V power supply ±5% Packaged in a JEDEC standard 100-pin TQFP package The IDT71V546 is a 3.3V high-speed 4,718,592-bit Megabit synchronous SRAM organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later its associated data cycle occurs, be it read or write. The IDT71V546 contains data I/O, address and control signal regis- ters. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable CEN pin allows operation of the IDT71V546 to be suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous values. There are three chip enable pins CE1, CE2, CE2 that allow the user to deselect the device when desired. If any one of these three is not active when ADV/LD is low, no new memory operation can be initiated and any burst that was in progress is stopped. However, any pending data transfers reads or writes will be completed. The data bus will tri-state two cycles after the chip is deselected or a write initiated. The IDT71V546 has an on-chip burst counter. In the burst mode, the IDT71V546 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address ADV/LD = LOW or increment the internal burst counter ADV/LD = HIGH . The IDT71V546 SRAM utilizes IDT's high-performance, high-volume 3.3V CMOS process, and is packaged in a JEDEC standard 14mm x 20mm 100- pin thin plastic quad flatpack TQFP for high board density. Pin Description Summary A0 - A16 Address Inputs CE1, CE2, CE2 OE Three Chip Enables Output Enable Read/Write Signal Clock Enable BW1, BW2, BW3, BW4 Individual Byte Write Selects CLK ADV/LD Clock Advance Burst Address / Load New Address Linear / Interleaved Burst Order I/O0 - I/O31, I/OP1 - I/OP4 Data Input/Output 3.3V Power Ground Input I/O Supply Synchronous Asynchronous Synchronous N/A Synchronous Ordering Information 71V546 Device Type Power Speed PF Package Process/ Temperature Range Blank I Commercial 0°C to +70°C Industrial -40°C to +85°C Restricted hazardous substance device 100 pin Plastic Thin Quad Flatpack PK100-1 Clock Frequency in Megahertz 100 Thin Quad Flatpack Packaging Blank First or current generation die step Current generation die step optional PART NUMBER tCD PARAMETER SPEED IN MEGAHERTZ CLOCK CYCLE TIME 71V546S133PF 71V546S117PF 71V546S100PF 133 MHz 117 MHz 100 MHz ns 10 ns 3821 drw 12 IDT71V546, 128K x 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Pipelined Outputs Datasheet Document History Commercial and Industrial Temperature Ranges 6/15/99 9/13/99 12/31/99 11/22/05 02/23/07 10/18/08 Pg. 12 Pg. 20 Pg. 3, 12, 13, 19 Pg. 3,4 Pg. 20 Pg. 20 Pg. 20 Updated to new format Corrected ISB3 conditions Added Datasheet Document History Added Industrial Temperature range offerings Moved Operating temperature & DC operating tables from page 3 to new page Moved Absolute rating & Capacitance tables from page 4 to new page Add clarification note to Recommended Operating Temperature and Absolute Max Ratings tables. Updated order information with "Restricted hazardous substance device" Added X generation die step to data sheet ordering information. Removed "IDT" from orderable part number CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax 408-284-2775 The IDT logo is a registered trademark of Integrated Device Technology, Inc. for Tech Support: 800-345-7015

PDF Datasheet Preview

128K x 36, 3.3V Synchronous IDT71V546S/XS SRAM with ZBT Feature, Burst Counter and Pipelined Outputs
128K x 36 memory configuration, pipelined outputs Supports high performance system speed - 133 MHz
ns Clock-to-Data Access ZBTTM Feature - No dead cycles between write and read
cycles Internally synchronized registered outputs eliminate the
need to control OE Single R/W READ/WRITE control pin Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications 4-word burst capability interleaved or linear Individual byte write BW1 - BW4 control May tie active Three chip enables for simple depth expansion Single 3.3V power supply ±5% Packaged in a JEDEC standard 100-pin TQFP package

The IDT71V546 is a 3.3V high-speed 4,718,592-bit Megabit synchronous SRAM organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around.

Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later its associated data cycle occurs, be it
read or write.

The IDT71V546 contains data I/O, address and control signal regis-
ters. Output enable is the only asynchronous signal and can be used to
disable the outputs at any given time. A Clock Enable CEN pin allows operation of the IDT71V546 to be
suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous
values. There are three chip enable pins CE1, CE2, CE2 that allow the user
to deselect the device when desired. If any one of these three is not active when ADV/LD is low, no new memory operation can be initiated and any
burst that was in progress is stopped. However, any pending data
transfers reads or writes will be completed. The data bus will tri-state two
cycles after the chip is deselected or a write initiated.

The IDT71V546 has an on-chip burst counter. In the burst mode, the

IDT71V546 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address ADV/LD = LOW or increment the internal burst counter ADV/LD = HIGH .

The IDT71V546 SRAM utilizes IDT's high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC standard 14mm x
20mm 100- pin thin plastic quad flatpack TQFP for high board density.

Pin Description Summary

A0 - A16

Address Inputs

CE1, CE2, CE2 OE

Three Chip Enables Output Enable

Read/Write Signal

Clock Enable

BW1, BW2, BW3, BW4 Individual Byte Write Selects

CLK ADV/LD

Clock Advance Burst Address / Load New Address

Linear / Interleaved Burst Order

I/O0 - I/O31, I/OP1 - I/OP4 Data Input/Output
3.3V Power

Ground

Input I/O Supply

Synchronous Asynchronous Synchronous

N/A Synchronous
Ordering Information
71V546

Device Type

Power Speed

PF Package

Process/ Temperature

Range

Blank I

Commercial 0°C to +70°C Industrial -40°C to +85°C

Restricted hazardous substance device
100 pin Plastic Thin Quad Flatpack PK100-1

Clock Frequency in Megahertz
100 Thin Quad Flatpack Packaging

Blank First or current generation die step

Current generation die step optional

PART NUMBER tCD PARAMETER SPEED IN MEGAHERTZ CLOCK CYCLE TIME
71V546S133PF 71V546S117PF 71V546S100PF
133 MHz 117 MHz 100 MHz
ns 10 ns
3821 drw 12

IDT71V546, 128K x 36, 3.3V Synchronous SRAM with ZBT Feature, Burst Counter and Pipelined Outputs

Datasheet Document History

Commercial and Industrial Temperature Ranges
6/15/99 9/13/99 12/31/99 11/22/05
02/23/07 10/18/08

Pg. 12 Pg. 20 Pg. 3, 12, 13, 19 Pg. 3,4

Pg. 20 Pg. 20 Pg. 20
Updated to new format Corrected ISB3 conditions Added Datasheet Document History Added Industrial Temperature range offerings Moved Operating temperature & DC operating tables from page 3 to new page Moved Absolute rating & Capacitance tables from page 4 to new page Add clarification note to Recommended Operating Temperature and Absolute Max Ratings tables. Updated order information with "Restricted hazardous substance device" Added X generation die step to data sheet ordering information. Removed "IDT" from orderable part number

CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200 fax 408-284-2775

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
for Tech Support:
800-345-7015

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT71V546S133PF8 Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT71V546S133PF8 637341