IDT71V2556S133PFI

IDT71V2556S133PFI Datasheet

IDT71V2556S/XS

Part	Datasheet
IDT71V2556S133PFI	IDT71V2556S133PFI (pdf)

Related Parts	Information
IDT71V2556S166PF8	IDT71V2556S166PF8
IDT71V2556XS133PF	IDT71V2556XS133PF
IDT71V2556S166PFI	IDT71V2556S166PFI
IDT71V2556S166PF	IDT71V2556S166PF
IDT71V2556S133PFI8	IDT71V2556S133PFI8
IDT71V2556XS133PF8	IDT71V2556XS133PF8
IDT71V2556S100PF	IDT71V2556S100PF
IDT71V2556S133PF	IDT71V2556S133PF
IDT71V2556S100PFI8	IDT71V2556S100PFI8
IDT71V2556S100PFI	IDT71V2556S100PFI
IDT71V2556S100PF8	IDT71V2556S100PF8
IDT71V2556S133PF8	IDT71V2556S133PF8
IDT71V2556S166PFI8	IDT71V2556S166PFI8

PDF Datasheet Preview
128K x 36, 256K x 18 IDT71V2556S/XS 3.3V Synchronous ZBT SRAMs IDT71V2558S/XS 2.5V I/O, Burst Counter IDT71V2556SA/XSA Pipelined Outputs IDT71V2558SA/XSA 128K x 36, 256K x 18 memory configurations Supports high performance system speed - 200 MHz ns Clock-to-Data Access ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R/W READ/WRITE control pin Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications 4-word burst capability interleaved or linear Individual byte write BW1 - BW4 control May tie active Three chip enables for simple depth expansion 3.3V power supply ±5% , 2.5V I/O Supply VDDQ Optional - Boundary Scan JTAG Interface IEEE complaint Packaged in a JEDEC standard 100-pin plastic thin quad flatpack TQFP , 119 ball grid array BGA and 165 fine pitch ball grid array fBGA The IDT71V2556/58 are 3.3V high-speed 4,718,592-bit Mega- bit synchronous SRAMS. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround. Address and control signals are applied to the SRAM during one clock Pin Description Summary A0-A17 Address Inputs cycle, and two cycles later the associated data cycle occurs, be it read or write. The IDT71V2556/58 contain data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable CEN pin allows operation of the IDT71V2556/58 to be suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous values. There are three chip enable pins CE1, CE2, CE2 that allow the user to deselect the device when desired. If any one of these three are not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers reads or writes will be completed. The data bus will tri-state two cycles after chip is deselected or a write is initiated. The IDT71V2556/58 has an on-chip burst counter. In the burst mode, the IDT71V2556/58 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address ADV/LD = LOW or increment the internal burst counter ADV/LD = HIGH . The IDT71V2556/58 SRAMs utilize IDT's latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack TQFP as well as a 119 ball grid array BGA and a 165 fine pitch ball grid array fBGA . Input Synchronous CE1, CE2, CE2 Chip Enables Input Synchronous Output Enable Input Asynchronous Read/Write Signal Ordering Information IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Datasheet Document History 6/30/99 8/23/99 10/4/99 12/31/99 04/30/00 05/26/00 07/26/00 10/25/00 5/20/02 10/15/04 02/23/07 10/13/08 05/24/10 Pp. 4, 5 Pg. 6 Pg. 14 Pg. 15 Pg. 22 Pg. 24 Pg. 14 Pg. 15 Pg. 5,6 Pg. 6 Pg. 7 Pg. 21 Pg. 23 Pg. 5,6,7 Pg. 8 Pg. 23 Pg. 8 Pg. 1-8,15,22,23,27 Pg.7 Pg.27 Pg.27 Pg.27 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Rd San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support 800-345-7015 or 408/284-4555 The IDT logo is a registered trademark of Integrated Device Technology, Inc. ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

PDF Datasheet Preview

128K x 36, 256K x 18

IDT71V2556S/XS
3.3V Synchronous ZBT SRAMs IDT71V2558S/XS
2.5V I/O, Burst Counter

IDT71V2556SA/XSA

Pipelined Outputs

IDT71V2558SA/XSA
128K x 36, 256K x 18 memory configurations Supports high performance system speed - 200 MHz
ns Clock-to-Data Access ZBTTM Feature - No dead cycles between write and read
cycles

Internally synchronized output buffer enable eliminates the need to control OE

Single R/W READ/WRITE control pin Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications 4-word burst capability interleaved or linear Individual byte write BW1 - BW4 control May tie active Three chip enables for simple depth expansion 3.3V power supply ±5% , 2.5V I/O Supply VDDQ Optional - Boundary Scan JTAG Interface IEEE
complaint Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack TQFP , 119 ball grid array BGA and 165 fine pitch
ball grid array fBGA

The IDT71V2556/58 are 3.3V high-speed 4,718,592-bit Mega-
bit synchronous SRAMS. They are designed to eliminate dead bus cycles
when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBTTM, or Zero Bus

Turnaround.

Address and control signals are applied to the SRAM during one clock

Pin Description Summary

A0-A17

Address Inputs
cycle, and two cycles later the associated data cycle occurs, be it read or write.

The IDT71V2556/58 contain data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time.

A Clock Enable CEN pin allows operation of the IDT71V2556/58 to be suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous values.

There are three chip enable pins CE1, CE2, CE2 that allow the user to deselect the device when desired. If any one of these three are not asserted when ADV/LD is low, no new memory operation can be initiated. However, any pending data transfers reads or writes will be completed. The data bus will tri-state two cycles after chip is deselected or a write is initiated.

The IDT71V2556/58 has an on-chip burst counter. In the burst mode, the IDT71V2556/58 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address ADV/LD = LOW or increment the internal burst counter ADV/LD = HIGH .

The IDT71V2556/58 SRAMs utilize IDT's latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack TQFP as well as a 119 ball grid array BGA and a 165 fine pitch ball grid array fBGA .

Input

Synchronous

CE1, CE2, CE2

Chip Enables

Input

Synchronous

Output Enable

Input

Asynchronous

Read/Write Signal
Ordering Information

IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

Datasheet Document History
6/30/99 8/23/99
10/4/99 12/31/99 04/30/00
05/26/00 07/26/00 10/25/00 5/20/02 10/15/04 02/23/07 10/13/08 05/24/10

Pp. 4, 5 Pg. 6 Pg. 14 Pg. 15

Pg. 22 Pg. 24 Pg. 14 Pg. 15

Pg. 5,6

Pg. 6 Pg. 7 Pg. 21

Pg. 23 Pg. 5,6,7 Pg. 8 Pg. 23

Pg. 8 Pg. 1-8,15,22,23,27 Pg.7

Pg.27 Pg.27 Pg.27
CORPORATE HEADQUARTERS 6024 Silver Creek Valley Rd San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support 800-345-7015 or 408/284-4555

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT71V2556S133PFI Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT71V2556S133PFI 637329