5T9955BFGI8

5T9955BFGI8 Datasheet

IDT5T9955 2.5V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W

Part	Datasheet
5T9955BFGI8	5T9955BFGI8 (pdf)

Related Parts	Information
5T9955BFGI	5T9955BFGI

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IDT5T9955 2.5V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W 2.5V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W INDUSTRIAL TEMPERATURE RANGE IDT5T9955 FEATURES: • Ref input is 3.3V tolerant • 8 pairs of programmable skew outputs • Low skew 185ps same pair, 250ps same bank, 350ps both banks • Selectable positive or negative edge synchronization on each bank excellent for DSP applications • Synchronous output enable on each bank • Input frequency 2MHz to 160MHz • Output frequency 6MHz to 160MHz • 3-level inputs for skew and PLL range control • 3-level inputs for feedback divide selection multiply / divide ratios of 1-6, 8, 10, 12 / 2, 4 • PLL bypass for DC testing • External feedback, internal loop filter • 12mA balanced drive outputs • Low Jitter <100ps cycle-to-cycle • Power-down mode on each bank • Lock indicator on each bank • Available in BGA package DESCRIPTION: The IDT5T9955 is a high fanout 2.5V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5T9955 has sixteen programmable skew outputs in eight banks of The two separate PLLs allow the user to independently control A and B banks. Skew is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. The feedback input allows divide-by-functionality from 1 to 12 through the use of the xDS[1:0] inputs. This provides the user with frequency multiplication from 1 to 12 without using divided outputs for feedback. When the xsOE pin is held low, all the xbank outputs are synchronously enabled. However, if xsOE is held high, all the xbank outputs except x2Q0 and x2Q1 are synchronously disabled. The xLOCK output is high when the xbank PLL has achieved phase lock. Furthermore, when xPE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When xPE is held low, all the outputs are synchronized with the negative edge of REF. The IDT5T9955 has LVTTL outputs with 12mA balanced drive outputs. FUNCTIONAL BLOCK DIAGRAM ALOCK AFS AsOE /N 33 A1Q0 A1Q1 Skew 3 Select 3 TEST AFB ADS1:0 A1F1:0 BFB BDS1:0 B1F1:0 A2Q0 A2Q1 3 Skew Select A2F1:0 B2F1:0 A3Q0 A3Q1 3 Skew Select 3 A3F1:0 B3F1:0 A4Q0 A4Q1 3 Skew Select 3 A4F1:0 B4F1:0 /N 33 BLOCK BsOE ORDERING INFORMATION Device Type Package INDUSTRIAL TEMPERATURE RANGE -40°C to +85°C Industrial BF BFG Fine Pitch Ball Grid Array FBGA - Green 5T9955 2.5V Programmable Skew Dual PLL Clock Driver TurboClock W CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support:

PDF Datasheet Preview

IDT5T9955 2.5V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
2.5V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W

INDUSTRIAL TEMPERATURE RANGE

IDT5T9955

FEATURES:
• Ref input is 3.3V tolerant
• 8 pairs of programmable skew outputs
• Low skew 185ps same pair, 250ps same bank, 350ps both
banks
• Selectable positive or negative edge synchronization on each
bank excellent for DSP applications
• Synchronous output enable on each bank
• Input frequency 2MHz to 160MHz
• Output frequency 6MHz to 160MHz
• 3-level inputs for skew and PLL range control
• 3-level inputs for feedback divide selection multiply / divide
ratios of 1-6, 8, 10, 12 / 2, 4
• PLL bypass for DC testing
• External feedback, internal loop filter
• 12mA balanced drive outputs
• Low Jitter <100ps cycle-to-cycle
• Power-down mode on each bank
• Lock indicator on each bank
• Available in BGA package

DESCRIPTION:

The IDT5T9955 is a high fanout 2.5V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5T9955 has sixteen programmable skew outputs in eight banks of The two separate PLLs allow the user to independently control A and B banks. Skew is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels.

The feedback input allows divide-by-functionality from 1 to 12 through the use of the xDS[1:0] inputs. This provides the user with frequency multiplication from 1 to 12 without using divided outputs for feedback.

When the xsOE pin is held low, all the xbank outputs are synchronously enabled. However, if xsOE is held high, all the xbank outputs except x2Q0 and x2Q1 are synchronously disabled. The xLOCK output is high when the xbank PLL has achieved phase lock.

Furthermore, when xPE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When xPE is held low, all the outputs are synchronized with the negative edge of REF. The IDT5T9955 has LVTTL outputs with 12mA balanced drive outputs.

FUNCTIONAL BLOCK DIAGRAM

ALOCK AFS

AsOE
/N 33

A1Q0 A1Q1

Skew 3

Select 3

TEST

AFB ADS1:0 A1F1:0

BFB BDS1:0 B1F1:0

A2Q0 A2Q1
3 Skew Select

A2F1:0

B2F1:0

A3Q0 A3Q1
3 Skew

Select 3

A3F1:0

B3F1:0

A4Q0 A4Q1
3 Skew

Select 3

A4F1:0

B4F1:0
/N 33

BLOCK

BsOE
ORDERING INFORMATION

Device Type Package

INDUSTRIAL TEMPERATURE RANGE
-40°C to +85°C Industrial

BF BFG

Fine Pitch Ball Grid Array FBGA - Green
5T9955 2.5V Programmable Skew Dual PLL Clock Driver TurboClock W

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 5T9955BFGI8 Datasheet file may be downloaded here without warranties.

Datasheet ID: 5T9955BFGI8 637285