5T93GL16NLGI8

5T93GL16NLGI8 Datasheet

IDT5T93GL16 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER II

Part	Datasheet
5T93GL16NLGI8	5T93GL16NLGI8 (pdf)

Related Parts	Information
5T93GL16NLGI	5T93GL16NLGI

PDF Datasheet Preview
IDT5T93GL16 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER II INDUSTRIAL TEMPERATURE RANGE 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER II IDT5T93GL16 FEATURES: • Guaranteed Low Skew < 25ps max • Very low duty cycle distortion < 100ps max • High speed propagation delay < 2ns max • Up to 650MHz operation • Glitchless input clock switching • Selectable inputs • Hot insertable and over-voltage tolerant inputs • 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL 2.5V , LVPECL 3.3V , CML, or LVDS input interface • Selectable differential inputs to sixteen LVDS outputs • Power-down mode • 2.5V VDD • Available in VFQFPN package APPLICATIONS: • Clock distribution DESCRIPTION: The IDT5T93GL16 2.5V differential clock buffer is a user-selectable differential input to sixteen LVDS outputs The fanout from a differential input to sixteen LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T93GL16 can act as a translator from a differential HSTL, eHSTL, LVEPECL 2.5V , LVPECL 3.3V , CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for a glitchless change-over from a primary clock source to a secondary clock source. Selectable inputs are controlled by SEL. During the switchover, the output will disable low for up to three clock cycles of the previously-selected input clock. The outputs will remain low for up to three clock cycles of the newlyselected clock, after which the outputs will start from the newly-selected input. A FSEL pin has been implemented to control the switchover in cases where a clock source is absent or is driven to DC levels below the minimum specifications. The IDT5T93GL16 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise. FUNCTIONAL BLOCK DIAGRAM GL G1 A2 SEL FSEL The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 2007 Integrated Device Technology, Inc. OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL Q16 JANUARY 2007 DSC 6185/19 IDT5T93GL16 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER II PIN CONFIGURATION INDUSTRIAL TEMPERATURE RANGE SEL VDD Q16 Q15 Q14 Q13 VDD PD FSEL 52 51 50 49 48 47 46 45 44 43 42 41 40 14 15 16 17 18 19 20 21 22 23 24 25 26 ORDERING INFORMATION Device Type Package Process INDUSTRIAL TEMPERATURE RANGE -40°C to +85°C Industrial NL NLG Thermally Enhanced Plastic Very Fine Pitch Quad Flat No Lead Package VFQFPN - Green 5T93GL16 2.5V LVDS 1:16 Glitchless Clock Buffer Terabuffer II CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support:

PDF Datasheet Preview

IDT5T93GL16 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER II

INDUSTRIAL TEMPERATURE RANGE
2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER II

IDT5T93GL16

FEATURES:
• Guaranteed Low Skew < 25ps max
• Very low duty cycle distortion < 100ps max
• High speed propagation delay < 2ns max
• Up to 650MHz operation
• Glitchless input clock switching
• Selectable inputs
• Hot insertable and over-voltage tolerant inputs
• 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL 2.5V , LVPECL 3.3V ,

CML, or LVDS input interface
• Selectable differential inputs to sixteen LVDS outputs
• Power-down mode
• 2.5V VDD
• Available in VFQFPN package

APPLICATIONS:
• Clock distribution

DESCRIPTION:

The IDT5T93GL16 2.5V differential clock buffer is a user-selectable differential input to sixteen LVDS outputs The fanout from a differential input to sixteen LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The IDT5T93GL16 can act as a translator from a differential HSTL, eHSTL, LVEPECL 2.5V , LVPECL 3.3V , CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for a glitchless change-over from a primary clock source to a secondary clock source. Selectable inputs are controlled by SEL. During the switchover, the output will disable low for up to three clock cycles of the previously-selected input clock. The outputs will remain low for up to three clock cycles of the newlyselected clock, after which the outputs will start from the newly-selected input. A FSEL pin has been implemented to control the switchover in cases where a clock source is absent or is driven to DC levels below the minimum specifications.

The IDT5T93GL16 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.

FUNCTIONAL BLOCK DIAGRAM GL G1

A2 SEL FSEL

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE
2007 Integrated Device Technology, Inc.

OUTPUT CONTROL

OUTPUT CONTROL

OUTPUT CONTROL

OUTPUT CONTROL

OUTPUT CONTROL

OUTPUT CONTROL

OUTPUT CONTROL

OUTPUT CONTROL

OUTPUT CONTROL

OUTPUT CONTROL

OUTPUT CONTROL

OUTPUT CONTROL

OUTPUT CONTROL

OUTPUT CONTROL

OUTPUT CONTROL

OUTPUT CONTROL

Q16 JANUARY 2007

DSC 6185/19

IDT5T93GL16 2.5V LVDS 1:16 GLITCHLESS CLOCK BUFFER TERABUFFER II

PIN CONFIGURATION

INDUSTRIAL TEMPERATURE RANGE

SEL VDD Q16 Q15 Q14 Q13 VDD PD FSEL
52 51 50 49 48 47 46 45 44 43 42 41 40
14 15 16 17 18 19 20 21 22 23 24 25 26
ORDERING INFORMATION

Device Type Package Process

INDUSTRIAL TEMPERATURE RANGE
-40°C to +85°C Industrial

NL NLG

Thermally Enhanced Plastic Very Fine Pitch Quad Flat No Lead Package VFQFPN - Green
5T93GL16 2.5V LVDS 1:16 Glitchless Clock Buffer Terabuffer II

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 5T93GL16NLGI8 Datasheet file may be downloaded here without warranties.

Datasheet ID: 5T93GL16NLGI8 637280