5P49EE601NLGI

5P49EE601NLGI Datasheet

IDT5P49EE601

Part	Datasheet
5P49EE601NLGI	5P49EE601NLGI (pdf)

Related Parts	Information
5P49EE601NLGI8	5P49EE601NLGI8

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LOW POWER CLOCK GENERATOR DATASHEET IDT5P49EE601 The IDT5P49EE601 is a programmable clock generator intended for low power, battery operated consumer applications. There are four internal PLLs, each individually programmable, allowing for up to six differrent output frequencies. The frequencies are generated from a single reference clock. The reference clock can come from either a TCXO or fundamental mode crystal. An additional 32.768kHz crystal oscillator is available to provide a real time clock or non-critical performance MHz processor clock. The IDT5P49EE601 can be programmed through the use of the I2C interfaces. The programming interface enables the device to be programmed when it is in normal operation or what is commonly known as in system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. Each of the four PLLs has an 8-bit reference divider and a 11-bit feedback divider. This allows the user to generate four unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation is supported on one of the PLLs. The device is specifically designed to work with display applications to ensure that the spread profile remains consistent for each HSYNC in order to reduce ROW noise. There are total five 8-bit output dividers. One output bank can be configured to support LVTTL or LVDS. All other outputs are always set to LVTTL. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function can be programmed. Target Applications • Smart Mobile Handset • Personal Navigation Device PND • Camcorder • DSC • Portable Game Console • Personal Media Player • Four internal PLLs • Internal non-volatile EEPROM • Internal I2C EEPROM master interface • FAST 400kHz mode I2C serial interfaces • Input Frequencies TCXO 10 MHz to 40 MHz Crystal 8 MHz to 30 MHz RTC Crystal kHz • Output Frequency Ranges kHz to 120 MHz • Each PLL has an 8-bit reference divider and a 11-bit feedback-divider • 8-bit output-divider blocks • One of the PLLs support Spread Spectrum generation capable of configuration to pixel rate, with adjustable modulation rate and amplitude to support video clock with no visible artifacts • I/O Standards: Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS Outputs - 1 pair selectable 3.3V LVDS • 3 independent adjustable VDDO groups. • Programmable Slew Rate Control • Programmable Loop Bandwidth Settings • Programmable output inversion to reduce bimodal jitter • Individual output enable/disable • Power-down/Sleep mode 10uA max in power down mode 32kHz clock output active sleep mode 100uA max in sleep mode • 1.8V VDD Core Voltage • Available in 24pin 4x4mm QFN packages • -40 to +85 C Industrial Temp operation LOW POWER CLOCK GENERATOR IDT5P49EE601 LOW POWER CLOCK GENERATOR Functional Block Diagram EEPROM CLOCK GENERATOR X IN /R E F XOUT SDA SCL SEL[1:0] 32kXIN 32kXOUT VDDO1 REFSELA PLLA C o n tro l Logic REFSELB PLLB SS REFSELC PLLC REFSELD PLLD VDDO2 VDDO3 /D IV 0 /D IV 1 Ordering Information Part / Order Number 5P49EE601NLGI 5P49EE601NLGI8 Marking See Page 23 See Page 23 Shipping Packaging Tubes Tape and Reel Package 24pin VFQFPN 24pin VFQFPN Temperature -40 to +85° C -40 to +85° C “G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology IDT assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. LOW POWER CLOCK GENERATOR IDT5P49EE601REV L 072512 IDT5P49EE601 LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR Date 10/29/09 11/20/09 3/25/10 6/11/10 9/08/10/29/10 01/19/11 04/13/11 05/04/11 09/30/11 10/17/11 07/25/12 Originator R.Willner R.Willner R.Willner R.Willner R.Willner R. Willner R. Willner R. Willner R. Willner R. Willner R. Willner R. Willner Description of Change Preliminary Datasheet release. No_PD bit inclusion - 32kHz clock on/off in Config Typographical changes. Correct spread spectrum calculations. Typographical changes. Default configuration. Input Clock max voltage swing 1.8V. Power ramp sequence. Typographical changes. Loop filter calculations. Default register bit corrections. Corrected notes for top-side marking. Updated SCLK and SDA pin descriptions Updated DC Electrical Char table for 1.8V LVTTL added VIH and VIL. Updated “Lock Time/PLL Lock Time from shutdown mode” Typ. and Max. specs in AC Timing Electrical Char table. Added Landing Pattern diagram. Updated Power-up/down sequence diagram notes. Added VDDOx specs to Recommended Operations table Updated Power-up/down Sequence diagrams Added pin 1 indicator dot on marking diagram. LOW POWER CLOCK GENERATOR IDT5P49EE601 LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: For Sales 800-345-7015 408-284-8200 Fax 408-284-2775 For Tech Support Corporate Headquarters Integrated Device Technology, Inc. 2011 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

PDF Datasheet Preview

LOW POWER CLOCK GENERATOR

DATASHEET

IDT5P49EE601

The IDT5P49EE601 is a programmable clock generator intended for low power, battery operated consumer applications. There are four internal PLLs, each individually programmable, allowing for up to six differrent output frequencies. The frequencies are generated from a single reference clock. The reference clock can come from either a TCXO or fundamental mode crystal. An additional 32.768kHz crystal oscillator is available to provide a real time clock or non-critical performance MHz processor clock.

The IDT5P49EE601 can be programmed through the use of the I2C interfaces. The programming interface enables the device to be programmed when it is in normal operation or what is commonly known as in system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up.

Each of the four PLLs has an 8-bit reference divider and a 11-bit feedback divider. This allows the user to generate four unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation.

Spread spectrum generation is supported on one of the PLLs. The device is specifically designed to work with display applications to ensure that the spread profile remains consistent for each HSYNC in order to reduce ROW noise.

There are total five 8-bit output dividers. One output bank can be configured to support LVTTL or LVDS. All other outputs are always set to LVTTL. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function can be programmed.

Target Applications
• Smart Mobile Handset
• Personal Navigation Device PND
• Camcorder
• DSC
• Portable Game Console
• Personal Media Player
• Four internal PLLs
• Internal non-volatile EEPROM
• Internal I2C EEPROM master interface
• FAST 400kHz mode I2C serial interfaces
• Input Frequencies

TCXO 10 MHz to 40 MHz Crystal 8 MHz to 30 MHz RTC Crystal kHz
• Output Frequency Ranges kHz to 120 MHz
• Each PLL has an 8-bit reference divider and a 11-bit
feedback-divider
• 8-bit output-divider blocks
• One of the PLLs support Spread Spectrum generation
capable of configuration to pixel rate, with adjustable modulation rate and amplitude to support video clock with no visible artifacts
• I/O Standards:

Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS Outputs - 1 pair selectable 3.3V LVDS
• 3 independent adjustable VDDO groups.
• Programmable Slew Rate Control
• Programmable Loop Bandwidth Settings
• Programmable output inversion to reduce bimodal jitter
• Individual output enable/disable
• Power-down/Sleep mode
10uA max in power down mode 32kHz clock output active sleep mode 100uA max in sleep mode
• 1.8V VDD Core Voltage
• Available in 24pin 4x4mm QFN packages
• -40 to +85 C Industrial Temp operation

LOW POWER CLOCK GENERATOR

IDT5P49EE601 LOW POWER CLOCK GENERATOR

Functional Block Diagram

EEPROM CLOCK GENERATOR

X IN /R E F XOUT

SDA SCL SEL[1:0]
32kXIN 32kXOUT

VDDO1

REFSELA

PLLA

C o n tro l Logic

REFSELB PLLB SS

REFSELC

PLLC

REFSELD PLLD

VDDO2

VDDO3
/D IV 0
/D IV 1
Ordering Information

Part / Order Number
5P49EE601NLGI 5P49EE601NLGI8

Marking

See Page 23 See Page 23

Shipping Packaging

Tubes Tape and Reel

Package
24pin VFQFPN 24pin VFQFPN

Temperature
-40 to +85° C -40 to +85° C
“G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology IDT assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

LOW POWER CLOCK GENERATOR

IDT5P49EE601REV L 072512

IDT5P49EE601 LOW POWER CLOCK GENERATOR

EEPROM CLOCK GENERATOR

Date 10/29/09 11/20/09 3/25/10 6/11/10 9/08/10/29/10 01/19/11 04/13/11
05/04/11 09/30/11 10/17/11
07/25/12

Originator R.Willner R.Willner R.Willner R.Willner R.Willner R. Willner R. Willner R. Willner

R. Willner R. Willner R. Willner

R. Willner

Description of Change Preliminary Datasheet release. No_PD bit inclusion - 32kHz clock on/off in Config Typographical changes. Correct spread spectrum calculations. Typographical changes. Default configuration. Input Clock max voltage swing 1.8V. Power ramp sequence. Typographical changes. Loop filter calculations. Default register bit corrections. Corrected notes for top-side marking. Updated SCLK and SDA pin descriptions Updated DC Electrical Char table for 1.8V LVTTL added VIH and VIL. Updated “Lock Time/PLL Lock Time from shutdown mode” Typ. and Max. specs in AC Timing Electrical Char table. Added Landing Pattern diagram. Updated Power-up/down sequence diagram notes. Added VDDOx specs to Recommended Operations table Updated Power-up/down Sequence diagrams Added pin 1 indicator dot on marking diagram.

LOW POWER CLOCK GENERATOR

IDT5P49EE601 LOW POWER CLOCK GENERATOR

EEPROM CLOCK GENERATOR

Innovate with IDT and accelerate your future networks. Contact:

For Sales
800-345-7015 408-284-8200 Fax 408-284-2775

For Tech Support

Corporate Headquarters

Integrated Device Technology, Inc.
2011 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 5P49EE601NLGI Datasheet file may be downloaded here without warranties.

Datasheet ID: 5P49EE601NLGI 637268