4EA1250A0Z4
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4EA1250A0Z4BACUGI (pdf) |
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4EA1250A0Z4AACUGI8 |
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4EA1250A0Z4AACUGI |
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4EA1250A0Z4BACUGI8 |
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Quad Freq LVDS+CMOS Oscillator 4EA1250A0Z4 125 / 150 / 200 / 250MHz with 50MHz CMOS ADVANCE DATASHEET • 4 LVDS Frequencies • 1 CMOS output • Frequency Stability • Supply Voltage • Standard Packages • RMS phase jitter • Operating Temperature: 125, 150, 200 & 250MHz 50MHz ± 50ppm 2.5V and 3.3V x mm 1 ps typical 12k to 20MHz - 40 to 85 °C x mm package The 4EA1250A0Z4 is a quad frequency oscillator incorporating IDT’s pMEMS technology to generate up to four LVDS clock frequencies. An additional synchronous CMOS output is also provided for general purpose clocking. One 4EA1250A0Z4 can replace up to 5 separate crystal oscillators, reducing inventory and bill-of-material cost. The pinout and footprint is backward compatible to industry standard 7050 size oscillators, ensuring second source compatibility to traditional 6 pin SMD oscillators. Functional Block Diagram Output Enable Frequency Select OE± OE_C MEMS IDT ASIC FS0 FS1 OUT- Diff Out OUT+ OE± CMOS OUTC OE_C LVDS CMOS 25MHz Pin Description Pin Name OE± LVDS Output Enable 6, 7 OUT+, OUT- LVDS Output No connect 3, 8 GND, VDD Supply Voltage 4, 5 FS0, FS1 Frequency Select OE_C CMOS Output Enable OUTC CMOS Output OUTC OE_C OE± 1 OUT- FS0 FS1 OUT+ Part Ordering Information Package Size Voltage Ordering Code 3.3V x mm 2.5V 4EA1250A0Z4AACUGI 4EA1250A0Z4BACUGI * Factory minimum order quantity 500pcs T/R Jan 24, 2013 Frequency Table Input* Output MHz FS[1,0] LVDS CMOS 1,0,1 * FS0, FS1 includes weak pull-up resistor Enable/Disable OE±* LVDS *Includes weak pull-up resistor OE_C* CMOS *Includes weak pull-down resistor Output Waveform CMOS VDD VOL SYM = t1 / t2 t1 t2 4EA 1250 A0 Z4 A CUG Frequency MHz Voltage A 3.3V B 2.5V Package Temperature Shipping CUG x I -40 to 85°C Blank Tubes 8 T/R 2013 Integrated Device Technology, Inc Quad Freq LVDS+CMOS OscillatorDatasheet Specification Parameter Supply Voltage VDD Frequency Stability Supply Current Enable/Disable Time Input HIGH/LOW level Start-up Time Aging Output LOW level Output HIGH level Amplitude VA Mid Level VM Rise Time TR Fall Time TF Symmetry SYM Phase Jitter Period Jitter Cycle-to-Cycle Jitter Rise/Fall Time TR/ TF Symmetry SYM Output HIGH/LOW level Period Jitter rms Cycle to Cycle Jitter V Specifications Min Typ Max 7VDD 0.3VDD |
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