IDT2305-1HDC

IDT2305-1HDC Datasheet

IDT2305 3.3V ZERO DELAY CLOCK BUFFER

Part	Datasheet
IDT2305-1HDC	IDT2305-1HDC (pdf)

Related Parts	Information
IDT2305-1HDCI8	IDT2305-1HDCI8
IDT2305-1DC	IDT2305-1DC
IDT2305-1DC8	IDT2305-1DC8
IDT2305-1DCI	IDT2305-1DCI
IDT2305-1DCI8	IDT2305-1DCI8
IDT2305-1HDCI	IDT2305-1HDCI
IDT2305-1HDC8	IDT2305-1HDC8

PDF Datasheet Preview
IDT2305 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 3.3V ZERO DELAY CLOCK BUFFER IDT2305 FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five outputs • Zero Input-Output Delay • Output Skew < 250ps • Low jitter <200 ps cycle-to-cycle • IDT2305-1 for Standard Drive • IDT2305-1H for High Drive • No external RC network required • Operates at 3.3V VDD • Power down mode • Available in SOIC package DESCRIPTION: The IDT2305 is a high-speed phase-lock loop PLL clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2305 is an 8-pin version of the IDT2309. IDT2305 accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates, up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT2305 enters power down. In this mode, the device will draw less than 25uA, the outputs are tri-stated, and the PLL is not running, resulting in a significant reduction of power. The IDT2305 is characterized for both Industrial and Commercial operation. FUNCTIONAL BLOCK DIAGRAM 1 REF PLL Control Logic 8 CLKOUT 3 CLK1 2 CLK2 5 CLK3 7 CLK4 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL c 2007 Integrated Device Technology, Inc. TEMPERATURE 1 RANGES DECEMBER 2007 DSC 5174/8 IDT2305 3.3V ZERO DELAY CLOCK BUFFER PIN CONFIGURATION CLK2 CLK1 SOIC TOP VIEW APPLICATIONS: • SDRAM • Telecom • Datacom • PC Motherboards/Workstations • Critical Path Delay Designs CLKOUT CLK4 VDD CLK3 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS 1 Rating Max. Unit Supply Voltage Range Input Voltage Range REF to V ORDERING INFORMATION Device Type Package Process COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Blank I Commercial 0oC to +70oC Industrial -40oC to +85oC DC DCG Small Outline SOIC - Green 2305-1 Zero Delay Clock Buffer 2305-1H High Drive Output IDT2305-1DC IDT2305-1DCG IDT2305-1DCI IDT2305-1DCGI IDT2305-1HDC IDT2305-1HDCI Ordering Code 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC Package Type Commercial Industrial Commercial Industrial Operating Range CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 for Tech Support:

PDF Datasheet Preview

IDT2305 3.3V ZERO DELAY CLOCK BUFFER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY CLOCK BUFFER

IDT2305

FEATURES:
• Phase-Lock Loop Clock Distribution
• 10MHz to 133MHz operating frequency
• Distributes one clock input to one bank of five outputs
• Zero Input-Output Delay
• Output Skew < 250ps
• Low jitter <200 ps cycle-to-cycle
• IDT2305-1 for Standard Drive
• IDT2305-1H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Power down mode
• Available in SOIC package

DESCRIPTION:

The IDT2305 is a high-speed phase-lock loop PLL clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.

The IDT2305 is an 8-pin version of the IDT2309. IDT2305 accepts one reference input, and drives out five low skew clocks. The -1H version of this device operates, up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT2305 enters power down. In
this mode, the device will draw less than 25uA, the outputs are tri-stated,
and the PLL is not running, resulting in a significant reduction of power. The IDT2305 is characterized for both Industrial and Commercial
operation.

FUNCTIONAL BLOCK DIAGRAM
1 REF

PLL Control Logic
8 CLKOUT
3 CLK1
2 CLK2
5 CLK3
7 CLK4

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL
c 2007 Integrated Device Technology, Inc.

TEMPERATURE 1

RANGES

DECEMBER 2007

DSC 5174/8

IDT2305 3.3V ZERO DELAY CLOCK BUFFER

PIN CONFIGURATION

CLK2

CLK1

SOIC TOP VIEW

APPLICATIONS:
• SDRAM
• Telecom
• Datacom
• PC Motherboards/Workstations
• Critical Path Delay Designs

CLKOUT CLK4 VDD CLK3

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS 1

Rating

Max. Unit

Supply Voltage Range

Input Voltage Range REF to V
ORDERING INFORMATION

Device Type Package Process

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

Blank I

Commercial 0oC to +70oC Industrial -40oC to +85oC

DC DCG

Small Outline SOIC - Green
2305-1 Zero Delay Clock Buffer 2305-1H High Drive Output

IDT2305-1DC IDT2305-1DCG IDT2305-1DCI IDT2305-1DCGI IDT2305-1HDC IDT2305-1HDCI
Ordering Code
8-Pin SOIC 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC 8-Pin SOIC

Package Type

Commercial Industrial Commercial Industrial

Operating Range

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775
for Tech Support:

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT2305-1HDC Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT2305-1HDC 637243