VF2510BGLF

VF2510BGLF Datasheet

ICSVF2510

Part	Datasheet
VF2510BGLF	VF2510BGLF (pdf)

Related Parts	Information
VF2510BGT	VF2510BGT
VF2510BGLN	VF2510BGLN
VF2510BGLFT	VF2510BGLFT
VF2510BGILF	VF2510BGILF
VF2510BGILFT	VF2510BGILFT
VF2510BGLNT	VF2510BGLNT
VF2510BG	VF2510BG

PDF Datasheet Preview
Integrated Circuit Systems, Inc. ICSVF2510 3.3V Phase-Lock Loop Clock Driver The ICSVF2510 is a high performance, low skew, low jitter • Meets or exceeds PC133 registered DIMM clock driver. It uses a phase lock loop PLL technology to specification1.1 align, in both phase and frequency, the CLKIN signal with the CLKOUT signal. It is specifically designed for use with synchronous SDRAMs.The ICSVF2510 operates at 3.3V • • Spread Spectrum Clock Compatible Distributes one clock input to one bank of ten outputs VCC and drives up to ten clock loads. • Operating frequency 20MHz to 200MHz One bank of ten outputs provide low-skew, low-jitter copies of CLKIN. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLKIN. • • External feedback input FBIN terminal is used to synchrionize the outputs to the clock input No external RC network required Outputs can be enabled or disabled via control OE • Operates at 3.3V Vcc inputs. When the OE inputs are high, the outputs align in phase and frequency with CLKIN when the OE inputs are Plastic 24-pin 173mil TSSOP package low, the outputs are disabled to the logic low state. The ICSVF2510 does not require external RC filter components.The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. The test mode shuts off the PLL and connects the input directly to the output buffer.This test mode, the ICSVF2510 can be use as low skew fanout clock buffer device. The ICSVF2510 comes in 24 pin 173mil Thin Shrink SmallOutline package TSSOP package. Block Diagram FBIN PLL CLKIN AVCC FBOUT CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 CLK9 Pin Configuration AGND 1 VCC 2 CLK0 3 CLK1 4 CLK2 5 GND 6 GND 7 CLK3 8 CLK4 9 VCC 10 OE 11 FBOUT 12 ICSVF2510 24 CLKIN 23 AVCC 22 VCC 21 CLK9 20 CLK8 19 GND 18 GND 17 CLK7 16 CLK6 15 CLK5 14 VCC 13 FBIN 24 Pin TSSOP mm. Body, mm. Pitch ICSVF2510 Pin Descriptions PIN # 1 2, 10, 14 3 4 5 6, 7, 18, 19 8 9 PIN NAME AGND VCC CLK0 CLK1 CLK2 GND CLK3 CLK4 FBOUT FBIN CLK5 CLK6 Ordering Information ICSVF2510yG-T Example: ICS XXXX y G - PPP - T Designation for tape and reel packaging Pattern Number 2 or 3 digit number for parts with ROM code patterns Package Type ICS, AV = Standard Device

PDF Datasheet Preview

Integrated Circuit Systems, Inc.

ICSVF2510
3.3V Phase-Lock Loop Clock Driver

The ICSVF2510 is a high performance, low skew, low jitter
• Meets or exceeds PC133 registered DIMM
clock driver. It uses a phase lock loop PLL technology to
specification1.1
align, in both phase and frequency, the CLKIN signal with the CLKOUT signal. It is specifically designed for use with synchronous SDRAMs.The ICSVF2510 operates at 3.3V
•
•

Spread Spectrum Clock Compatible Distributes one clock input to one bank of ten outputs

VCC and drives up to ten clock loads.
• Operating frequency 20MHz to 200MHz

One bank of ten outputs provide low-skew, low-jitter copies of CLKIN. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLKIN.
•
•

External feedback input FBIN terminal is used to synchrionize the outputs to the clock input

No external RC network required

Outputs can be enabled or disabled via control OE
• Operates at 3.3V Vcc
inputs. When the OE inputs are high, the outputs align in phase and frequency with CLKIN when the OE inputs are

Plastic 24-pin 173mil TSSOP package
low, the outputs are disabled to the logic low state.

The ICSVF2510 does not require external RC filter components.The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. The test mode shuts off the PLL and connects the input directly to the output buffer.This test mode, the ICSVF2510 can be use as low skew fanout clock buffer device. The ICSVF2510 comes in 24 pin 173mil Thin Shrink SmallOutline package TSSOP package.

Block Diagram

FBIN PLL

CLKIN AVCC

FBOUT CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 CLK9

Pin Configuration

AGND 1 VCC 2 CLK0 3 CLK1 4 CLK2 5 GND 6 GND 7 CLK3 8 CLK4 9 VCC 10 OE 11

FBOUT 12

ICSVF2510
24 CLKIN 23 AVCC 22 VCC 21 CLK9 20 CLK8 19 GND 18 GND 17 CLK7 16 CLK6 15 CLK5 14 VCC 13 FBIN
24 Pin TSSOP
mm. Body, mm. Pitch

ICSVF2510

Pin Descriptions

PIN # 1
2, 10, 14 3 4 5
6, 7, 18, 19 8 9

PIN NAME AGND VCC CLK0 CLK1 CLK2 GND CLK3 CLK4

FBOUT

FBIN

CLK5

CLK6
Ordering Information

ICSVF2510yG-T

Example:

ICS XXXX y G - PPP - T

Designation for tape and reel packaging Pattern Number 2 or 3 digit number for parts with ROM code patterns Package Type

ICS, AV = Standard Device

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Datasheet ID: VF2510BGLF 637239