ICS9112AG-27

ICS9112AG-27 Datasheet

ICS9112-27

Part	Datasheet
ICS9112AG-27	ICS9112AG-27 (pdf)

Related Parts	Information
ICS9112AG-27T	ICS9112AG-27T

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ICS9112-27 Low Skew PCI / PCI-X Buffer The ICS9112-27 is a high performance, low skew, low jitter PCI / PCI-X clock driver. It is designed to distribute high speed signals in PCI / PCI-X applications operating at speeds from 0 to 140 MHz. The ICS9112-27 is characterized for operation from -40°C to 85°C for automotive and industrial applications. • Frequency range 0 - 140 MHz 3.3V • Less than 200 ps Jitter between outputs • Skew controlled outputs < 100 ps • Distribute one clock input to one bank of four outputs • 3.3V ±10% operation • Available in 8 pin TSSOP, and SOIC packages. Block Diagram LOGIC CONTROL CLK_IN Pin Descriptions PIN NUMBER 1 PIN NAME CLK_IN CLK0 CLK1 CLK2 CLK3 CLK0 CLK1 CLK2 CLK3 ICS9112-27 Pin Configuration CLK_IN 1 OE 2 CLK0 3 GND 4 8 CLK3 7 CLK2 6 VDD 5 CLK1 8 pin TSSOP & SOIC Functionality Table INPUTS CLK_IN OUTPUTS CLK 3:0 Tristate 0 Tristate TYPE IN OUT PWR OUT PWR OUT DESCRIPTION Input reference frequency. Output enable. When OE is low, it tristates the clock outputs Buffered clock output Ground Buffered clock output Power supply for 3.3V Buffered clock output Buffered clock output ICS9112-27 Absolute Maximum Ratings Supply voltage range VDD -0.5V to V Input voltage range VI see notes 1 & 2 -0.5V to VDD + 0.5V Output voltage range VO see notes 1 & 2 -0.5V to VDD + 0.5V Input clamp current IIK VI< 0 or VI >VDD ±50 mA Output clamp current IOK VO< 0 or VO ±50 mA Continuous total output current, IO VO = 0 to VDD ±50 mA Package thermal impedance ØJA see note 3 PW package230.5°C/W Storage temperature rante, Tstg -65°C to 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Notes 1.The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to V maximum. The package thermal impedance is calculated in accordance with JESD Recommended Operating Conditions Supply voltage, VDD High-level input voltage, VIH Low-level input voltage, VIL Input voltage, VI High-level output current, IOH Low-level output current, IOL Operating free-air temperature, TA Min 3 0.7XVDD 0 Ordering Information 9112AG-27LF-T Example: XXXX A G LF- T Designation for tape and reel packaging Annealed Lead Free Optional Package Type ICS9112-27 INDEX AREA h x 45° A A1 SEATING PLANE 150 mil Narrow Body SOIC 150 mil Narrow Body SOIC In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS SEE VARIATIONS SEE VARIATIONS BASIC BASIC SEE VARIATIONS SEE VARIATIONS VARIATIONS D mm. Reference Doc. JEDEC Publication 95, MS-012 10-0030 D inch Ordering Information 9112AM-27LF-T Example: XXXX A M LF- T Designation for tape and reel packaging Annealed Lead Free Optional Package Type

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ICS9112-27

Low Skew PCI / PCI-X Buffer

The ICS9112-27 is a high performance, low skew, low jitter PCI / PCI-X clock driver. It is designed to distribute high speed signals in PCI / PCI-X applications operating at speeds from 0 to 140 MHz.

The ICS9112-27 is characterized for operation from -40°C to 85°C for automotive and industrial applications.
• Frequency range 0 - 140 MHz 3.3V
• Less than 200 ps Jitter between outputs
• Skew controlled outputs < 100 ps
• Distribute one clock input to one bank of four
outputs
• 3.3V ±10% operation
• Available in 8 pin TSSOP, and SOIC packages.

Block Diagram

LOGIC CONTROL

CLK_IN

Pin Descriptions

PIN NUMBER 1

PIN NAME CLK_IN

CLK0

CLK1

CLK2

CLK3

CLK0 CLK1 CLK2 CLK3

ICS9112-27

Pin Configuration

CLK_IN 1 OE 2

CLK0 3 GND 4
8 CLK3 7 CLK2 6 VDD 5 CLK1
8 pin TSSOP & SOIC

Functionality Table

INPUTS

CLK_IN

OUTPUTS CLK 3:0 Tristate
0 Tristate

TYPE IN

OUT PWR OUT PWR OUT

DESCRIPTION Input reference frequency. Output enable. When OE is low, it tristates the clock outputs

Buffered clock output Ground Buffered clock output Power supply for 3.3V Buffered clock output Buffered clock output

ICS9112-27

Absolute Maximum Ratings

Supply voltage range VDD -0.5V to V Input voltage range VI see notes 1 & 2 -0.5V to VDD + 0.5V Output voltage range VO see notes 1 & 2 -0.5V to VDD + 0.5V Input clamp current IIK VI< 0 or VI >VDD ±50 mA Output clamp current IOK VO< 0 or VO ±50 mA Continuous total output current, IO VO = 0 to VDD ±50 mA Package thermal impedance ØJA see note 3 PW package230.5°C/W Storage temperature rante, Tstg -65°C to 150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Notes 1.The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to V maximum. The package thermal impedance is calculated in accordance with JESD

Recommended Operating Conditions

Supply voltage, VDD High-level input voltage, VIH Low-level input voltage, VIL Input voltage, VI High-level output current, IOH Low-level output current, IOL Operating free-air temperature, TA

Min 3
0.7XVDD 0
Ordering Information
9112AG-27LF-T

Example:

XXXX A G LF- T

Designation for tape and reel packaging Annealed Lead Free Optional Package Type

ICS9112-27

INDEX AREA
h x 45° A A1

SEATING

PLANE
150 mil Narrow Body SOIC
150 mil Narrow Body SOIC

In Millimeters

In Inches

SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS

SEE VARIATIONS

SEE VARIATIONS

BASIC

BASIC

SEE VARIATIONS

SEE VARIATIONS

VARIATIONS

D mm.

Reference Doc. JEDEC Publication 95, MS-012 10-0030

D inch
Ordering Information
9112AM-27LF-T

Example:

XXXX A M LF- T

Designation for tape and reel packaging Annealed Lead Free Optional Package Type

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ICS9112AG-27 Datasheet file may be downloaded here without warranties.

Datasheet ID: ICS9112AG-27 637211