ICS843002BY-31LF

ICS843002BY-31LF Datasheet

ICS843002-31

Part	Datasheet
ICS843002BY-31LF	ICS843002BY-31LF (pdf)

Related Parts	Information
ICS843002BY-31LFT	ICS843002BY-31LFT

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FEMTOCLOCKS VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR ICS843002-31 The ICS843002-31 is a member of the HiperClockS family of high performance clock HiPerClockS solutions from IDT. This monolithic device is a high- performance, PLL-based synchronous clock generator and jitter attenuation circuit. The ICS843002-31 contains two clock multiplication stages that are cascaded in series. The first stage is a VCXO-based PLL that is optimized to provide reference clock jitter attenuation, to be jitter tolerant, and to provide a stable reference clock for the second multiplication stage. The second stage is the proprietary IDT FemtoClock circuit which is a high-frequency, sub- picosecond clock multiplier. The VCXO PLL has an on-chip VCXO circuit that uses an external, inexpensive pullable crystal in the to 25MHz range. The PLL includes 13 bit reference and feedback dividers supporting complex PLL multiplication ratios and input reference clock rates as low as 2.3kHz. External loop filter components are used two resistors and two capacitors to achieve the low loop bandwidth needed for jitter attenuation of a recovered data clock. The FemtoClock circuit can multiply the VCXO crystal frequency by a factor of 28 or 32 selectable and provide a clock output of up to 700MHz. Clock Input/Output Configuration: • Clock Inputs - one differential pair, two singled ended mux selected • Differential input pair can support LVPECL, LVDS, LVHSTL, SSTL, HCSL or single-ended LVCMOS or LVTTL levels • Singled ended inputs can support LVCMOS or LVTTL levels • Clock Outputs, FemtoClockS two LVPECL pairs selectable output dividers • Clock Output, VCXO one single ended output at VCXO crystal frequency • Clock Output, other VCXO reference clock Example Applications: • SONET/SDH line card clock generator up to 622.08MHz for OC-48 using 8kHz frame clock as input reference • Jitter attenuation of a recovered communications clock • Complex-ratio clock frequency translation between various communication protocols, such as • For telecom, OC-12 to E3 rate conversion, 622.08MHz to 34.368MHz, PLL ratio of 179/32 • For digital video, ITU-R601 to SMPTE 252M/59.94, 27MHz to 74.17582MHz, PLL ratio of 250/91 • Outputs • Two high frequency differential LVPECL outputs Output frequency up to 700MHz • One LVCMOS/LVTTL VCXO PLL output with output enable • One Reference clock output with output enable • One LOCK detect output • Input mux supports 3 selectable inputs one differential input pair and two LVCMOS/LVTTL input clocks • 13-bit VCXO PLL feedback and reference dividers provide wide range of frequency translation ratio options • FemtoClock frequency multiplier supports rate of 560MHz - 700MHz • ‘Lock Detect’ output reports lock status of VCXO PLL • VCXO PLL circuit provides jitter attenuation with loop bandwidth of 250Hz and below user adjustable • RMS phase jitter, random at 12kHz to 20MHz <1ps design target • 3.3V supply voltage • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request • Available in both standard RoHS 5 and lead-free RoHS 6 packages PIN ASSIGNMENT VCCA_XO XTAL_IN XTAL_OUT XOFB0 XOFB1 XOFB2 XOFB3 XOFB4 XOFB5 XOFB6 XOFB7 XOFB8 XOFB9 XOFB10 XOFB11 XOFB12 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 LF1 1 48 VEE TABLE ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843002CY-31 ICS843002CY31 64 Lead TQFP, EPAD tray 0°C to 70°C ICS843002CY-31T ICS843002CY31 64 Lead TQFP, EPAD 500 tape & reel 0°C to 70°C ICS843002CY-31LF 64 Lead "Lead-Free" TQFP, EPAD tray 0°C to 70°C ICS843002CY-31LFT 64 Lead "Lead-Free" TQFP, EPAD 500 tape & reel 0°C to 70°C NOTE Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated IDT assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT / ICS VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 27 ICS843002-31 FEMTOCLOCKS VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR Innovate with IDT and accelerate your future networks. Contact: For Sales 800-345-7015 408-284-8200 Fax 408-284-2775 For Tech Support 480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 outside U.S. Asia Pacific and Japan Integrated Device Technology Singapore 1997 Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 0 1372 363 339 Fax +44 0 1372 378851 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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FEMTOCLOCKS VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR

ICS843002-31

The ICS843002-31 is a member of the

HiperClockS family of high performance clock

HiPerClockS solutions from IDT. This monolithic device is a high-
performance, PLL-based synchronous clock
generator and jitter attenuation circuit. The

ICS843002-31 contains two clock multiplication stages that are
cascaded in series. The first stage is a VCXO-based PLL that
is optimized to provide reference clock jitter attenuation, to be
jitter tolerant, and to provide a stable reference clock for the
second multiplication stage. The second stage is the proprietary

IDT FemtoClock circuit which is a high-frequency, sub-
picosecond clock multiplier.

The VCXO PLL has an on-chip VCXO circuit that uses an external, inexpensive pullable crystal in the to 25MHz range. The PLL includes 13 bit reference and feedback dividers supporting complex PLL multiplication ratios and input reference clock rates as low as 2.3kHz. External loop filter components are used two resistors and two capacitors to achieve the low loop bandwidth needed for jitter attenuation of a recovered data clock.

The FemtoClock circuit can multiply the VCXO crystal frequency by a factor of 28 or 32 selectable and provide a clock output of up to 700MHz.

Clock Input/Output Configuration:
• Clock Inputs - one differential pair, two singled ended mux selected
• Differential input pair can support LVPECL, LVDS, LVHSTL, SSTL, HCSL or single-ended LVCMOS or LVTTL levels
• Singled ended inputs can support LVCMOS or LVTTL levels
• Clock Outputs, FemtoClockS two LVPECL pairs selectable output dividers
• Clock Output, VCXO one single ended output at VCXO crystal frequency
• Clock Output, other VCXO reference clock

Example Applications:
• SONET/SDH line card clock generator up to 622.08MHz for OC-48 using 8kHz frame clock as input reference
• Jitter attenuation of a recovered communications clock
• Complex-ratio clock frequency translation between various communication protocols, such as
• For telecom, OC-12 to E3 rate conversion, 622.08MHz to 34.368MHz, PLL ratio of 179/32
• For digital video, ITU-R601 to SMPTE 252M/59.94, 27MHz to 74.17582MHz, PLL ratio of 250/91
• Outputs
• Two high frequency differential LVPECL outputs Output frequency up to 700MHz
• One LVCMOS/LVTTL VCXO PLL output with output enable
• One Reference clock output with output enable
• One LOCK detect output
• Input mux supports 3 selectable inputs one differential input pair and two LVCMOS/LVTTL input clocks
• 13-bit VCXO PLL feedback and reference dividers provide wide range of frequency translation ratio options
• FemtoClock frequency multiplier supports rate of 560MHz - 700MHz
• ‘Lock Detect’ output reports lock status of VCXO PLL
• VCXO PLL circuit provides jitter attenuation with
loop bandwidth of 250Hz and below user adjustable
• RMS phase jitter, random at 12kHz to 20MHz <1ps design target
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Available in both standard RoHS 5 and lead-free RoHS 6
packages

PIN ASSIGNMENT

VCCA_XO XTAL_IN XTAL_OUT XOFB0 XOFB1 XOFB2 XOFB3 XOFB4 XOFB5 XOFB6 XOFB7 XOFB8 XOFB9 XOFB10 XOFB11 XOFB12
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

LF1 1
48 VEE
TABLE ORDERING INFORMATION

Part/Order Number

Marking

Package

Shipping Packaging Temperature

ICS843002CY-31

ICS843002CY31
64 Lead TQFP, EPAD
tray
0°C to 70°C

ICS843002CY-31T

ICS843002CY31
64 Lead TQFP, EPAD
500 tape & reel
0°C to 70°C

ICS843002CY-31LF
64 Lead "Lead-Free" TQFP, EPAD
tray
0°C to 70°C

ICS843002CY-31LFT
64 Lead "Lead-Free" TQFP, EPAD
500 tape & reel
0°C to 70°C

NOTE Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated IDT assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

IDT / ICS VCXO FREQUENCY TRANSLATOR/JITTER ATTENUATOR 27

ICS843002-31 FEMTOCLOCKS VCXO BASED FREQUENCY TRANSLATOR/JITTER ATTENUATOR

Innovate with IDT and accelerate your future networks. Contact:

For Sales
800-345-7015 408-284-8200 Fax 408-284-2775

For Tech Support
480-763-2056

Corporate Headquarters

Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 outside U.S.

Asia Pacific and Japan

Integrated Device Technology Singapore 1997 Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505

Europe

IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 0 1372 363 339 Fax +44 0 1372 378851
2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ICS843002BY-31LF Datasheet file may be downloaded here without warranties.

Datasheet ID: ICS843002BY-31LF 637100