ICS673M-01IT

ICS673M-01IT Datasheet


ICS673-01

Part Datasheet
ICS673M-01IT ICS673M-01IT ICS673M-01IT (pdf)
Related Parts Information
ICS673M-01I ICS673M-01I ICS673M-01I
ICS673M-01 ICS673M-01 ICS673M-01
ICS673M-01T ICS673M-01T ICS673M-01T
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PLL BUILDING BLOCK

DATASHEET

ICS673-01

The ICS673-01 is a low cost, high-performance Phase Locked Loop PLL designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator VCO , and two output buffers. One output buffer is a divide by two of the other. Through the use of external reference and VCO dividers the ICS674-01 , the user can customize the clock to lock to a wide variety of input frequencies.

The ICS673-01 also has an output enable function that puts both outputs into a high-impedance state. The chip also has a power-down feature which turns off the entire device.

For applications that require low jitter or jitter attenuation, see the MK2069.
• Packaged in 16-pin SOIC
• Available in RoHS compliant package
• Access to VCO input and feedback paths of PLL
• Output operating range up to 120 MHz 5 V
• Able to lock MHz range outputs to kHz range inputs
through the use of external dividers
• Output Enable tri-states outputs
• Low skew output clocks
• Power-down turns off chip
• VCO predivide to feedback divider of 1 or 4
• 25 mA output drive capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• Single supply V ±5% or +5 V ±10% operating
voltage
• Industrial and commercial temperature ranges
• Forms a complete PLL, using the ICS674-01
• For better jitter performance, use the MK1575

Block Diagram

Clock Input

REFIN FBIN

PD entire chip

CHCP VCOIN VDD

Phase/ Frequency Detector

DOWN
1 MUX

External Feedback Divider such as the ICS674-01

OE both outputs

CLK1 CLK2

IDT / ICS PLL BUILDING BLOCK

ICS673-01 PLL BUILDING BLOCK

PLL BUILDING BLOCK

Pin Assignment

F B IN

CHGP

VC O IN

R EFIN

CLK1

CLK2

VCO Predivide Select Table

VCO Predivide
0 = connect pin directly to ground 1 = connect pin directly to VDD
16 pin narrow 150 m il S O IC

Pin Descriptions

Pin Number
2 3 4 5 6 7 8 9 10
13 14 15 16

Pin Name
Ordering Information

A1 -C-

SEATING PLANE

Part / Order Number
673M-01I 673M-01IT 673M-01ILF 673M-01ILFT 673M-01 673M-01T 673M-01LF 673M-01LFT

Marking

ICS673M-01I ICS673M-01I 673M-01ILF 673M-01ILF ICS673M-01 ICS673M-01 673M-01LF 673M-01LF

Shipping Packaging

Tubes Tape and Reel

Tubes Tape and Reel

Tubes Tape and Reel

Tubes Tape and Reel

Package
16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC

Temperature
-40 to +85° C -40 to +85° C -40 to +85° C -40 to +85° C 0 to +70° C 0 to +70° C 0 to +70° C 0 to +70° C

Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems ICS assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.

IDT / ICS PLL BUILDING BLOCK

ICS673-01 PLL BUILDING BLOCK

PLL BUILDING BLOCK

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Datasheet ID: ICS673M-01IT 637061