ICS571MT

ICS571MT Datasheet

ICS571

Part	Datasheet
ICS571MT	ICS571MT (pdf)

Related Parts	Information
ICS571M	ICS571M

PDF Datasheet Preview
LOW PHASE NOISE ZERO DELAY BUFFER DATASHEET ICS571 The ICS571 is a high speed, high output drive, low phase noise Zero Delay Buffer ZDB which integrates IDT’s proprietary analog/digital Phase Locked Loop PLL techniques. IDT introduced the world standard for these devices in 1992 with the debut of the AV9170, and updated that with the ICS570. The ICS571, part of IDT’s ClockBlocks family, was designed to operate at higher frequencies, with faster rise and fall times, and with lower phase noise. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both outputs, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other. The chip is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to video. By allowing offchip feedback paths, the ICS571 can eliminate the delay through other devices. The use of dividers in the feedback path will enable the part to multiply by more than two. • Packaged in 8-pin SOIC Pb free available • Can function as low phase noise x2 multiplier • Low skew outputs. One is ÷2 of other • Input clock frequency up to 160 MHz at V • Phase noise of better than -100 dBc/Hz from 1 kHz to 1 MHz offset from carrier • Can recover poor input clock duty cycle • Output clock duty cycle of 45/55 at V • High drive strength for >100 MHz outputs • Full CMOS clock swings with 25 mA drive capability at TTL levels • Advanced, low power CMOS process • Operating voltages of to V NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Block Diagram IDT / ICS LOW PHASE NOISE ZERO DELAY BUFFER ICS571 ICS571 LOW PHASE NOISE ZERO DELAY BUFFER Pin Assignment ZDB AND MULTIPLIER/DIVIDER Feedback Configuration Table and Frequency Ranges at V Feedback From CLK/2 Input clock frequency 2x Input clock frequency CLK/2 Input clock frequency/2 Input clock frequency Input Range 20 to 160 MHz 10 to 80 MHz Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 Pin Name ICLK VDD GND CLK/2 GND VDD CLK FBIN Pin Type CI P O P O CI Pin Description Reference clock input. Connect to V or +5 V. Must be same as other VDD. Connect to ground. Clock output per table above. Low skew divide by two of pin 7 clock. Connect to ground. Connect to V or +5 V. Must be same as other VDD. Clock output per table above. Feedback clock input. Connect to CLK or CLK/2 per table above. Key CI = clock input I = input O = output P = power supply connection. IDT / ICS LOW PHASE NOISE ZERO DELAY BUFFER ICS571 ICS571 LOW PHASE NOISE ZERO DELAY BUFFER ZDB AND MULTIPLIER/DIVIDER External Components The ICS571 requires a minimum number of external components for proper operation. Ordering Information A1 -C- SEATING PLANE Part / Order Number 571M* 571MT* 571MLF 571MLFT Marking ICS571M 571MLF Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Package 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC Temperature 0 to +70° C 0 to +70° C 0 to +70° C 0 to +70° C *NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01 Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology IDT assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT / ICS LOW PHASE NOISE ZERO DELAY BUFFER ICS571 ICS571 LOW PHASE NOISE ZERO DELAY BUFFER ZDB AND MULTIPLIER/DIVIDER Innovate with IDT and accelerate your future networks. Contact: For Sales 800-345-7015 408-284-8200 Fax 408-284-2775 For Tech Support Corporate Headquarters Integrated Device Technology, Inc. 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

PDF Datasheet Preview

LOW PHASE NOISE ZERO DELAY BUFFER

DATASHEET

ICS571

The ICS571 is a high speed, high output drive, low phase noise Zero Delay Buffer ZDB which integrates IDT’s proprietary analog/digital Phase Locked Loop PLL techniques. IDT introduced the world standard for these devices in 1992 with the debut of the AV9170, and updated that with the ICS570. The ICS571, part of IDT’s ClockBlocks family, was designed to operate at higher frequencies, with faster rise and fall times, and with lower phase noise. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both outputs, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other.

The chip is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to video. By allowing offchip feedback paths, the ICS571 can eliminate the delay through other devices. The use of dividers in the feedback path will enable the part to multiply by more than two.
• Packaged in 8-pin SOIC Pb free available
• Can function as low phase noise x2 multiplier
• Low skew outputs. One is ÷2 of other
• Input clock frequency up to 160 MHz at V
• Phase noise of better than -100 dBc/Hz from 1 kHz to 1

MHz offset from carrier
• Can recover poor input clock duty cycle
• Output clock duty cycle of 45/55 at V
• High drive strength for >100 MHz outputs
• Full CMOS clock swings with 25 mA drive capability at

TTL levels
• Advanced, low power CMOS process
• Operating voltages of to V

NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01

Block Diagram

IDT / ICS LOW PHASE NOISE ZERO DELAY BUFFER

ICS571

ICS571 LOW PHASE NOISE ZERO DELAY BUFFER

Pin Assignment

ZDB AND MULTIPLIER/DIVIDER

Feedback Configuration Table and Frequency Ranges at V

Feedback From

CLK/2

Input clock frequency 2x Input clock frequency

CLK/2

Input clock frequency/2 Input clock frequency

Input Range
20 to 160 MHz 10 to 80 MHz

Pin Descriptions

Pin Number
1 2 3 4 5 6 7 8

Pin Name

ICLK VDD GND CLK/2 GND VDD CLK FBIN

Pin Type

CI P O P O CI

Pin Description

Reference clock input. Connect to V or +5 V. Must be same as other VDD. Connect to ground. Clock output per table above. Low skew divide by two of pin 7 clock. Connect to ground. Connect to V or +5 V. Must be same as other VDD. Clock output per table above. Feedback clock input. Connect to CLK or CLK/2 per table above.

Key CI = clock input I = input O = output P = power supply connection.

IDT / ICS LOW PHASE NOISE ZERO DELAY BUFFER

ICS571

ICS571 LOW PHASE NOISE ZERO DELAY BUFFER

ZDB AND MULTIPLIER/DIVIDER

External Components

The ICS571 requires a minimum number of external components for proper operation.
Ordering Information

A1 -C-

SEATING PLANE

Part / Order Number
571M* 571MT* 571MLF 571MLFT

Marking

ICS571M
571MLF

Shipping Packaging

Tubes Tape and Reel

Tubes Tape and Reel

Package
8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC

Temperature
0 to +70° C 0 to +70° C 0 to +70° C 0 to +70° C
*NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01

Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology IDT assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

IDT / ICS LOW PHASE NOISE ZERO DELAY BUFFER

ICS571

ICS571 LOW PHASE NOISE ZERO DELAY BUFFER

ZDB AND MULTIPLIER/DIVIDER

Innovate with IDT and accelerate your future networks. Contact:

For Sales
800-345-7015 408-284-8200 Fax 408-284-2775

For Tech Support

Corporate Headquarters

Integrated Device Technology, Inc.
2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ICS571MT Datasheet file may be downloaded here without warranties.

Datasheet ID: ICS571MT 637021