1893YI-10LF

1893YI-10LF Datasheet

ICS1893Y-10

Part	Datasheet
1893YI-10LF	1893YI-10LF (pdf)

Related Parts	Information
1893YI-10LFT	1893YI-10LFT
ICS1893Y-10T	ICS1893Y-10T
ICS1893YI-10	ICS1893YI-10
ICS1893YI-10T	ICS1893YI-10T

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Integrated Circuit Systems, Inc. ICS1893Y-10 Document Type Data Sheet Document Stage Release 3.3-V 10Base-T/100Base-TX Integrated PHYceiver General The ICS1893Y-10 is a low-power, physical-layer device PHY that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection CSMA/CD Ethernet standards. The ICS1893Y-10 architecture is based on the ICS1892. The ICS1893Y-10 supports managed or unmanaged node, repeater, and switch applications. The ICS1893Y-10 incorporates digital signal processing DSP in its Physical Medium Dependent PMD sublayer. As a result, it can transmit and receive data on unshielded twisted-pair UTP category 5 cables with attenuation in excess of 24 dB at 100 MHz. With this ICS-patented technology, the ICS1893Y-10 can virtually eliminate errors from killer packets. The ICS1893Y-10 provides a Serial Management Interface for exchanging command and status information with a Station Management STA entity. The ICS1893Y-10 Media Dependent Interface MDI can be configured to provide either half- or full-duplex operation at data rates of 10 MHz or 100 MHz. The MDI configuration can be established manually with input pins or control register settings or automatically using the Auto-Negotiation features . When the ICS1893Y-10 Auto-Negotiation sublayer is enabled, it exchanges technology capability data with its remote link partner and automatically selects the highest-performance operating mode they have in common. • Supports category 5 cables with attenuation in excess of 24 dB at 100 MHz • Fully integrated, DSP-based PMD includes: Adaptive equalization and baseline wander correction Transmit wave shaping and stream cipher scrambler MLT-3 encoder and NRZ/NRZI encoder • Low-power, 0.35-micron CMOS typically 400 mW • Single 3.3-V power supply. • Single-chip, fully integrated PHY provides PCS, PMA, PMD, and AUTONEG sublayers of IEEE standard • 10Base-T and 100Base-TX IEEE compliant • Highly configurable design supports: Node, repeater, and switch applications Managed and unmanaged applications 10M or 100M half- and full-duplex modes Parallel detection Auto-negotiation, with Next Page capabilities • MAC/Repeater Interface can be configured as: 10M or 100M Media Independent Interface 100M Symbol Interface bypasses the PCS 10M 7-wire Serial Interface • Small Footprint 64-pin Thin Quad Flat Pack TQFP • Available in Industrial Temperature and Lead-Free ICS1893Y-10 Block 10/100 MII or Alternate MAC/Repeater Interface Interface MUX MII Serial Management Interface MII Extended Register PCS • Frame • CRS/COL Detection • Parallel to Serial • 4B/5B Low-Jitter Clock Synthesizer Clock 100Base-T PMA • Clock Recovery • Link Monitor • Signal Detection • Error Detection 10Base-T TP_PMD • MLT-3 • Stream Cipher • Adaptive Equalizer • Baseline Wander Correction Configuration and Status Integrated Switch AutoNegotiation TwistedPair Physical Dimensions of ICS1893Y-10 Package 147 Ordering 149 Copyright 2004, Integrated Circuit Systems, Inc. All rights reserved. January, 2004 ICS1893Y-10 - Release Page Document status changes from ‘Preliminary’ to ‘Release’. Also, change to text in bullet that starts with “Low-power”. renumbering. Chapter 8, “Pin Diagram, Listings, and Descriptions”. ICS1893Y-10 pin names have changes. Table 9-1 reflects changes to ICS1893Y-10 pin names. Table 9-2 reflects changes to ICS1893Y-10 pin names. Section “DC Operating Characteristics for Supply Current”. Changes to text and table reflect changes to ICS1893Y-10 pin names. Section “DC Operating Characteristics for TTL Inputs and Outputs”. Changes to text and table reflect changes to ICS1893Y-10 pin names. Table Changes to table values. Table Changes to table values. Table Changes to table values. Table title added. Table Changes to table values. Section “100M MII Carrier Assertion/De-Assertion Half-Duplex Transmission ”. Changes to table values and timing diagram. Section “10M MII Carrier Assertion/De-Assertion Half-Duplex Transmission ”. Changes to table values and timing diagram. Table Changes to table values. Also, the value that was previously ‘TBD’ is now determined. Table Changes to table values. Table Changes to table values. Table Changes to table values. Table Changes to table values. Table Changes to table values. Chapter 10, “Physical Dimensions of ICS1893Y-10 Package”. Changes to text in bullets. Copyright 2004, Integrated Circuit Systems, Inc. All rights reserved. January, 2004 ICS1893Y-10 Data Sheet - Release are made. For an explanation of change bars, see the Change Bar note on this page. The following list also indicates where changes occur. Table of Contents reflect page renumbering. Table 3-1 value xxx changes from 000011b to 000100b Section “Twisted-Pair Interface” text changes. Section “Twisted-Pair Transmitter Interface” and Section “Twisted-Pair Receiver Interface” are two new sections with two new figures. Section “Clock Reference Interface” reflects deletion of references to crystal oscillator, as the ICS1893Y-10 does not work with a crystal. Section and Section are deleted. Section “Status Interface” has two new notes, Notes 5 and A new figure, Figure 5-4, follows Section “Status Interface”. Table 7-9 value changes from F420 to F441. Section “Manufacturer's Model Number bits text changes. Table 7-10 value changes from 0000 to In the following areas, ICS1894 changes to ICS1893Y-10: • Section “Remote Jabber Detect bit • Table 8-5 RXCLK pin description. • Table 8-6 RXCLK pin description. • Table 8-8 NC pin description. In the following sections, pin 54 changes from VDD_IO to VDD • Section “ICS1893Y-10 Pin Diagram” • Section “ICS1893Y-10 Pin Listings” • Section “Ground and Power Pins” Table 8-4 text changes for the REF_IN and REF_OUT pin descriptions. Table 8-7 text changes for the RXTRI pin descriptions. Section “Ground and Power Pins” adds the VSS ground pin, pin Section “Recommended Component Values” text changes. A new figure, Figure 9-1, follows Section “Recommended Component Values”. Copyright 2004, Integrated Circuit Systems, Inc. All rights reserved. January, 2004 ICS1893Y-10 - Release occur. addition, changed “Supply Current Reset” IDD from 50 to 10 Typ and from 60 to 11 Max . Figure 11-1, “Package Type” added YI-10 = 10x10 TQFP Thin Quad Flat Pack , Industrial Temp. Copyright 2004, Integrated Circuit Systems, Inc. All rights reserved. January, 2004 ICS1893Y-10 Data Sheet - Release changes occur. Table of Contents reflect page renumbering. Table 8-18 to correct Bit definition Figure to add Lead-Free Section add Crystal Operation Copyright 2004, Integrated Circuit Systems, Inc. All rights reserved. January, 2004 ICS1893Y-10 - Release Chapter 1 Abbreviations and Acronyms Chapter 1 Abbreviations and Acronyms Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet. Table Abbreviations and Acronyms Abbreviation / Acronym Interpretation 4B/5B 4-Bit / 5-Bit Encoding/Decoding ANSI American National Standards Institute Chapter 11 Ordering Information Chapter 11 Ordering Information Figure ICS1893Y-10 Ordering Information Part / Order Number Marking ICS1893Y-10 1893Y-10 ICS1893YI-10 1893YI-10 ICS1893Y-10LF 1893Y-10LF ICS1893YI-10LF 1893YI-10LF Package 10x10 TQFP Thin Quad Flat Pack 10x10 TQFP Thin Quad Flat Pack 10x10 TQFP Lead Free 10x10 TQFP Lead Free Temperature 0° C to 70° C -40° C to 85° C 0° C to 70° C -40° C to 85° C Copyright 2004, Integrated Circuit Systems, Inc. All rights reserved. January, 2004 Integrated Circuit Systems, Inc. Corporate Headquarters Silicon Valley Web Site: 2435 Boulevard of the Generals Norristown, PA 19403 Telephone 610-630-5300 Fax: 610-630-5399 525 Race Street San Jose, CA 95126-3448 Telephone 408-297-1201 Fax: 408-925-9460 Email: ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

PDF Datasheet Preview

Integrated Circuit Systems, Inc.

ICS1893Y-10

Document Type Data Sheet Document Stage Release
3.3-V 10Base-T/100Base-TX Integrated PHYceiver

General

The ICS1893Y-10 is a low-power, physical-layer device PHY that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection CSMA/CD Ethernet standards. The ICS1893Y-10 architecture is based on the ICS1892. The ICS1893Y-10 supports managed or unmanaged node, repeater, and switch applications.

The ICS1893Y-10 incorporates digital signal processing DSP in its Physical Medium Dependent PMD sublayer. As a result, it can transmit and receive data on unshielded twisted-pair UTP category 5 cables with attenuation in excess of 24 dB at 100 MHz. With this ICS-patented technology, the ICS1893Y-10 can virtually eliminate errors from killer packets.

The ICS1893Y-10 provides a Serial Management Interface for exchanging command and status information with a Station Management STA entity.

The ICS1893Y-10 Media Dependent Interface MDI can be configured to provide either half- or full-duplex operation at data rates of 10 MHz or 100 MHz. The MDI configuration can be established manually with input pins or control register settings or automatically using the Auto-Negotiation features . When the ICS1893Y-10 Auto-Negotiation sublayer is enabled, it exchanges technology capability data with its remote link partner and automatically selects the highest-performance operating mode they have in common.
• Supports category 5 cables with attenuation in excess of
24 dB at 100 MHz
• Fully integrated, DSP-based PMD includes:

Adaptive equalization and baseline wander correction Transmit wave shaping and stream cipher scrambler MLT-3 encoder and NRZ/NRZI encoder
• Low-power, 0.35-micron CMOS typically 400 mW
• Single 3.3-V power supply.
• Single-chip, fully integrated PHY provides PCS, PMA,

PMD, and AUTONEG sublayers of IEEE standard
• 10Base-T and 100Base-TX IEEE compliant
• Highly configurable design supports:

Node, repeater, and switch applications Managed and unmanaged applications 10M or 100M half- and full-duplex modes Parallel detection Auto-negotiation, with Next Page capabilities
• MAC/Repeater Interface can be configured as:
10M or 100M Media Independent Interface 100M Symbol Interface bypasses the PCS 10M 7-wire Serial Interface
• Small Footprint 64-pin Thin Quad Flat Pack TQFP
• Available in Industrial Temperature and Lead-Free

ICS1893Y-10 Block
10/100 MII or Alternate

MAC/Repeater Interface

Interface MUX

MII Serial Management

Interface

MII Extended Register

PCS
• Frame
• CRS/COL

Detection
• Parallel to Serial
• 4B/5B

Low-Jitter Clock

Synthesizer

Clock
100Base-T

PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
10Base-T

TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander

Correction

Configuration and Status

Integrated Switch

AutoNegotiation

TwistedPair
Physical Dimensions of ICS1893Y-10 Package 147 Ordering 149

Copyright 2004, Integrated Circuit Systems, Inc. All rights reserved.

January, 2004

ICS1893Y-10 - Release

Page Document status changes from ‘Preliminary’ to ‘Release’. Also, change to text in bullet that starts with “Low-power”.
renumbering. Chapter 8, “Pin Diagram, Listings, and Descriptions”. ICS1893Y-10 pin names have changes. Table 9-1 reflects changes to ICS1893Y-10 pin names. Table 9-2 reflects changes to ICS1893Y-10 pin names. Section “DC Operating Characteristics for Supply Current”. Changes to text and table reflect
changes to ICS1893Y-10 pin names. Section “DC Operating Characteristics for TTL Inputs and Outputs”. Changes to text and table
reflect changes to ICS1893Y-10 pin names. Table Changes to table values. Table Changes to table values. Table Changes to table values. Table title added. Table Changes to table values. Section “100M MII Carrier Assertion/De-Assertion Half-Duplex Transmission ”. Changes to
table values and timing diagram. Section “10M MII Carrier Assertion/De-Assertion Half-Duplex Transmission ”. Changes to
table values and timing diagram. Table Changes to table values. Also, the value that was previously ‘TBD’ is now determined. Table Changes to table values. Table Changes to table values. Table Changes to table values. Table Changes to table values. Table Changes to table values. Chapter 10, “Physical Dimensions of ICS1893Y-10 Package”. Changes to text in bullets.

Copyright 2004, Integrated Circuit Systems, Inc. All rights reserved.

January, 2004

ICS1893Y-10 Data Sheet - Release
are made. For an explanation of change bars, see the Change Bar note on this page. The following list also indicates where changes occur.

Table of Contents reflect page renumbering. Table 3-1 value xxx changes from 000011b to 000100b Section “Twisted-Pair Interface” text changes. Section “Twisted-Pair Transmitter Interface” and Section “Twisted-Pair Receiver

Interface” are two new sections with two new figures. Section “Clock Reference Interface” reflects deletion of references to crystal oscillator, as the

ICS1893Y-10 does not work with a crystal. Section and Section are deleted. Section “Status Interface” has two new notes, Notes 5 and A new figure, Figure 5-4, follows Section “Status Interface”. Table 7-9 value changes from F420 to F441. Section “Manufacturer's Model Number bits text changes. Table 7-10 value changes from 0000 to In the following areas, ICS1894 changes to ICS1893Y-10:
• Section “Remote Jabber Detect bit
• Table 8-5 RXCLK pin description.
• Table 8-6 RXCLK pin description.
• Table 8-8 NC pin description. In the following sections, pin 54 changes from VDD_IO to VDD
• Section “ICS1893Y-10 Pin Diagram”
• Section “ICS1893Y-10 Pin Listings”
• Section “Ground and Power Pins” Table 8-4 text changes for the REF_IN and REF_OUT pin descriptions. Table 8-7 text changes for the RXTRI pin descriptions. Section “Ground and Power Pins” adds the VSS ground pin, pin Section “Recommended Component Values” text changes. A new figure, Figure 9-1, follows Section “Recommended Component Values”.

Copyright 2004, Integrated Circuit Systems, Inc. All rights reserved.

January, 2004

ICS1893Y-10 - Release
occur.
addition, changed “Supply Current Reset” IDD from 50 to 10 Typ and from 60 to 11 Max . Figure 11-1, “Package Type” added YI-10 = 10x10 TQFP Thin Quad Flat Pack , Industrial Temp.

Copyright 2004, Integrated Circuit Systems, Inc. All rights reserved.

January, 2004

ICS1893Y-10 Data Sheet - Release
changes occur.

Table of Contents reflect page renumbering. Table 8-18 to correct Bit definition Figure to add Lead-Free Section add Crystal Operation

Copyright 2004, Integrated Circuit Systems, Inc. All rights reserved.

January, 2004

ICS1893Y-10 - Release

Chapter 1 Abbreviations and Acronyms

Chapter 1 Abbreviations and Acronyms

Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet.

Table Abbreviations and Acronyms

Abbreviation / Acronym

Interpretation
4B/5B
4-Bit / 5-Bit Encoding/Decoding

ANSI

American National Standards Institute
Chapter 11 Ordering Information
Chapter 11 Ordering Information
Figure ICS1893Y-10 Ordering Information

Part / Order Number Marking

ICS1893Y-10
1893Y-10

ICS1893YI-10
1893YI-10

ICS1893Y-10LF 1893Y-10LF

ICS1893YI-10LF 1893YI-10LF

Package 10x10 TQFP Thin Quad Flat Pack 10x10 TQFP Thin Quad Flat Pack
10x10 TQFP Lead Free 10x10 TQFP Lead Free

Temperature 0° C to 70° C -40° C to 85° C 0° C to 70° C -40° C to 85° C

Copyright 2004, Integrated Circuit Systems, Inc. All rights reserved.

January, 2004

Integrated Circuit Systems, Inc.

Corporate Headquarters Silicon Valley Web Site:
2435 Boulevard of the Generals

Norristown, PA 19403

Telephone 610-630-5300

Fax:
610-630-5399
525 Race Street

San Jose, CA 95126-3448

Telephone 408-297-1201

Fax:
408-925-9460

Email:

ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 1893YI-10LF Datasheet file may be downloaded here without warranties.

Datasheet ID: 1893YI-10LF 636961