ICS1893Y-10

ICS1893Y-10 Datasheet

ICS1893

Part	Datasheet
ICS1893Y-10	ICS1893Y-10 (pdf)

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Integrated Circuit Systems, Inc. ICS1893 Document Type Data Sheet Document Stage Release 3.3-V 10Base-T/100Base-TX Integrated PHYceiver General The ICS1893 is a low-power, physical-layer device PHY that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection CSMA/CD Ethernet standards. The ICS1893 architecture is based on the ICS1892. The ICS1893 supports managed or unmanaged node, repeater, and switch applications. The ICS1893 incorporates digital signal processing DSP in its Physical Medium Dependent PMD sublayer. As a result, it can transmit and receive data on unshielded twisted-pair UTP category 5 cables with attenuation in excess of 24 dB at 100 MHz. With this ICS-patented technology, the ICS1893 can virtually eliminate errors from killer packets. The ICS1893 provides a Serial Management Interface for exchanging command and status information with a Station Management STA entity. The ICS1893 Media Dependent Interface MDI can be configured to provide either half- or full-duplex operation at data rates of 10 MHz or 100 MHz. The MDI configuration can be established manually with input pins or control register settings or automatically using the Auto-Negotiation features . When the ICS1893 Auto-Negotiation sublayer is enabled, it exchanges technology capability data with its remote link partner and automatically selects the highest-performance operating mode they have in common. • Supports category 5 cables with attenuation in excess of 24 dB at 100 MHz across a temperature range from -5°to +85°C • DSP-based baseline wander correction to virtually eliminate killer packets across temperature range of from -5°to +85°C • Low-power, 0.35-micron CMOS typically 400 mW • Single 3.3-V power supply. • Single-chip, fully integrated PHY provides PCS, PMA, PMD, and AUTONEG sublayers of IEEE standard • 10Base-T and 100Base-TX IEEE compliant • Fully integrated, DSP-based PMD includes: Adaptive equalization and baseline wander correction Transmit wave shaping and stream cipher scrambler MLT-3 encoder and NRZ/NRZI encoder • Highly configurable design supports: Node, repeater, and switch applications Managed and unmanaged applications 10M or 100M half- and full-duplex modes Parallel detection Auto-negotiation, with Next Page capabilities • MAC/Repeater Interface can be configured as: 10M or 100M Media Independent Interface 100M Symbol Interface bypasses the PCS 10M 7-wire Serial Interface • Small Footprint 64-pin Thin Quad Flat Pack TQFP NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01. ICS1893 Block Diagram 10/100 MII or Alternate MAC/Repeater Interface MII Serial Management Interface Interface MUX MII Extended Register PCS • Frame • CRS/COL Detection • Parallel to Serial • 4B/5B Low-Jitter Clock Synthesizer Clock 100Base-T PMA • Clock Recovery • Link Monitor • Signal Detection • Error Detection 10Base-T TP_PMD • MLT-3 • Stream Cipher • Adaptive Equalizer • Baseline Wander Correction Configuration and Status Ordering Information 151 Copyright 2000, Integrated Circuit Systems, Inc. All rights reserved. June, 2000 ICS1893 - Release Page Document status changes from ‘Preliminary’to ‘Release’. Also, change to text in bullet that starts with “Low-power”. renumbering. Chapter 9, “Pin Diagram, Listings, and Descriptions”. ICS1893 pin names have changes. Table 10-1 reflects changes to ICS1893 pin names. Table 10-2 reflects changes to ICS1893 pin names. Section “DC Operating Characteristics for Supply Current”. Changes to text and table reflect changes to ICS1893 pin names. Section “DC Operating Characteristics for TTL Inputs and Outputs”. Changes to text and table reflect changes to ICS1893 pin names. Table Changes to table values. Table Changes to table values. Table Changes to table values. Table title added. Table Changes to table values. Section “100M MII Carrier Assertion/De-Assertion Half-Duplex Transmission ”. Changes to table values and timing diagram. Section “10M MII Carrier Assertion/De-Assertion Half-Duplex Transmission ”. Changes to table values and timing diagram. Table Changes to table values. Also, the value that was previously ‘TBD’is now determined. Table Changes to table values. Table Changes to table values. Table Changes to table values. Table Changes to table values. Table Changes to table values. Chapter 11, “Physical Dimensions of ICS1893 Package”. Changes to text in bullets. Copyright 2000, Integrated Circuit Systems, Inc. All rights reserved. June, 2000 ICS1893 Data Sheet - Release are made. For an explanation of change bars, see the Change Bar note on this page. The following list also indicates where changes occur. Table of Contents reflect page renumbering. Table 3-1 value xxx changes from 000011b to 000100b Section “Twisted-Pair Interface”text changes. Section “Twisted-Pair Transmitter Interface”and Section “Twisted-Pair Receiver Interface”are two new sections with two new figures. Section “Clock Reference Interface”reflects deletion of references to crystal oscillator, as the ICS1893 does not work with a crystal. Section and Section are deleted. Section “Status Interface”has two new notes, Notes 5 and A new figure, Figure 6-3, follows Section “Status Interface”. Table 8-9 value changes from F420 to F441. Section “Manufacturer's Model Number bits 3.9:4 ”text changes. Table 8-10 value changes from 0000 to In the following areas, ICS1894 changes to ICS1893: • Section “Remote Jabber Detect bit • Table 9-5 RXCLK pin description. • Table 9-6 RXCLK pin description. • Table 9-8 NC pin description. In the following sections, pin 54 changes from VDD_IO to VDD • Section “ICS1893 Pin Diagram” • Section “ICS1893 Pin Listings” • Section “Ground and Power Pins” Table 9-4 text changes for the REF_IN and REF_OUT pin descriptions. Table 9-7 text changes for the RXTRI pin descriptions. Section “Ground and Power Pins”adds the VSS ground pin, pin Section “Recommended Component Values”text changes. A new figure, Figure 10-1, follows Section “Recommended Component Values” Change Bars Change bars on subsequent ICS1893 data sheets indicate new documents posted to the web. Change bars within a new version of a document also indicates changes to the document. Copyright 2000, Integrated Circuit Systems, Inc. All rights reserved. June, 2000 ICS1893 - Release Chapter 1 Abbreviations and Acronyms Chapter 1 Abbreviations and Acronyms Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet. Table Abbreviations and Acronyms Abbreviation / Acronym Interpretation 4B/5B 4-Bit / 5-Bit Encoding/Decoding ANSI American National Standards Institute CMOS complimentary metal-oxide semiconductor CSMA/CD Carrier Sense Multiple Access with Collision Detection Command Override Write digital signal processing End-of-Stream Delimiter FDDI Fiber Distributed Data Interface frequency-locked loop Fast Link Pulse A ‘dead’time on the link following a 10Base-T packet, not to be confused with idle International Electrotechnical Commission IEEE Institute of Electrical and Electronic Engineers International Standards Organization Latching High Latching Low Latching Maximum Media Access Control Max. maximum Mbps Megabits per second Media Dependent Interface Management Frame Media Independent Interface Min. Chapter 12 Ordering Information NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01. Figure 12-1 shows ordering information for the ICS1893 package: • ICS1893Y-10 and ICS1893YI-10 industrial temp. Figure ICS1893 Ordering Information ICS 1893 Y -10 Chapter 12 Ordering Information Package Type Y-10 = 10 x 10 TQFP Thin Quad Flat Pack Device Identifier Company Identifier Integrated Circuit Systems, Inc. Copyright 2000, Integrated Circuit Systems, Inc. All rights reserved. June, 2000 Integrated Circuit Systems, Inc. Corporate Headquarters Silicon Valley Web Site: 2435 Boulevard of the Generals P.O. Box 968 Valley Forge, PA 19482-0968 Telephone 610-630-5300 Fax: 610-630-5399 525 Race Street San Jose, CA 95126-3448 Telephone 408-297-1201 Fax: 408-925-9460 Email: ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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Integrated Circuit Systems, Inc.

ICS1893

Document Type Data Sheet Document Stage Release
3.3-V 10Base-T/100Base-TX Integrated PHYceiver

General

The ICS1893 is a low-power, physical-layer device PHY that supports the ISO/IEC 10Base-T and 100Base-TX Carrier-Sense Multiple Access/Collision Detection CSMA/CD Ethernet standards. The ICS1893 architecture is based on the ICS1892. The ICS1893 supports managed or unmanaged node, repeater, and switch applications.

The ICS1893 incorporates digital signal processing DSP in its Physical Medium Dependent PMD sublayer. As a result, it can transmit and receive data on unshielded twisted-pair UTP category 5 cables with attenuation in excess of 24 dB at 100 MHz. With this ICS-patented technology, the ICS1893 can virtually eliminate errors from killer packets.

The ICS1893 provides a Serial Management Interface for exchanging command and status information with a Station Management STA entity.

The ICS1893 Media Dependent Interface MDI can be configured to provide either half- or full-duplex operation at data rates of 10 MHz or 100 MHz. The MDI configuration can be established manually with input pins or control register settings or automatically using the Auto-Negotiation features . When the ICS1893 Auto-Negotiation sublayer is enabled, it exchanges technology capability data with its remote link partner and automatically selects the highest-performance operating mode they have in common.
• Supports category 5 cables with attenuation in excess of
24 dB at 100 MHz across a temperature range from -5°to +85°C
• DSP-based baseline wander correction to virtually
eliminate killer packets across temperature range of from -5°to +85°C
• Low-power, 0.35-micron CMOS typically 400 mW
• Single 3.3-V power supply.
• Single-chip, fully integrated PHY provides PCS, PMA,

PMD, and AUTONEG sublayers of IEEE standard
• 10Base-T and 100Base-TX IEEE compliant
• Fully integrated, DSP-based PMD includes:

Adaptive equalization and baseline wander correction Transmit wave shaping and stream cipher scrambler MLT-3 encoder and NRZ/NRZI encoder
• Highly configurable design supports:

Node, repeater, and switch applications Managed and unmanaged applications 10M or 100M half- and full-duplex modes Parallel detection Auto-negotiation, with Next Page capabilities
• MAC/Repeater Interface can be configured as:
10M or 100M Media Independent Interface 100M Symbol Interface bypasses the PCS 10M 7-wire Serial Interface
• Small Footprint 64-pin Thin Quad Flat Pack TQFP

NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01.

ICS1893 Block Diagram
10/100 MII or Alternate

MAC/Repeater Interface

MII Serial Management

Interface

Interface MUX

MII Extended Register

PCS
• Frame
• CRS/COL

Detection
• Parallel to Serial
• 4B/5B

Low-Jitter Clock

Synthesizer

Clock
100Base-T

PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
10Base-T

TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander

Correction

Configuration and Status
Ordering Information 151

Copyright 2000, Integrated Circuit Systems, Inc. All rights reserved.

June, 2000

ICS1893 - Release

Page Document status changes from ‘Preliminary’to ‘Release’. Also, change to text in bullet that starts with “Low-power”.
renumbering. Chapter 9, “Pin Diagram, Listings, and Descriptions”. ICS1893 pin names have changes. Table 10-1 reflects changes to ICS1893 pin names. Table 10-2 reflects changes to ICS1893 pin names. Section “DC Operating Characteristics for Supply Current”. Changes to text and table reflect
changes to ICS1893 pin names. Section “DC Operating Characteristics for TTL Inputs and Outputs”. Changes to text and
table reflect changes to ICS1893 pin names. Table Changes to table values. Table Changes to table values. Table Changes to table values. Table title added. Table Changes to table values. Section “100M MII Carrier Assertion/De-Assertion Half-Duplex Transmission ”. Changes
to table values and timing diagram. Section “10M MII Carrier Assertion/De-Assertion Half-Duplex Transmission ”. Changes to
table values and timing diagram. Table Changes to table values. Also, the value that was previously ‘TBD’is now determined. Table Changes to table values. Table Changes to table values. Table Changes to table values. Table Changes to table values. Table Changes to table values. Chapter 11, “Physical Dimensions of ICS1893 Package”. Changes to text in bullets.

Copyright 2000, Integrated Circuit Systems, Inc. All rights reserved.

June, 2000

ICS1893 Data Sheet - Release
are made. For an explanation of change bars, see the Change Bar note on this page. The following list also indicates where changes occur.

Table of Contents reflect page renumbering. Table 3-1 value xxx changes from 000011b to 000100b Section “Twisted-Pair Interface”text changes. Section “Twisted-Pair Transmitter Interface”and Section “Twisted-Pair Receiver

Interface”are two new sections with two new figures. Section “Clock Reference Interface”reflects deletion of references to crystal oscillator, as the

ICS1893 does not work with a crystal. Section and Section are deleted. Section “Status Interface”has two new notes, Notes 5 and A new figure, Figure 6-3, follows Section “Status Interface”. Table 8-9 value changes from F420 to F441. Section “Manufacturer's Model Number bits 3.9:4 ”text changes. Table 8-10 value changes from 0000 to In the following areas, ICS1894 changes to ICS1893:
• Section “Remote Jabber Detect bit
• Table 9-5 RXCLK pin description.
• Table 9-6 RXCLK pin description.
• Table 9-8 NC pin description. In the following sections, pin 54 changes from VDD_IO to VDD
• Section “ICS1893 Pin Diagram”
• Section “ICS1893 Pin Listings”
• Section “Ground and Power Pins” Table 9-4 text changes for the REF_IN and REF_OUT pin descriptions. Table 9-7 text changes for the RXTRI pin descriptions. Section “Ground and Power Pins”adds the VSS ground pin, pin Section “Recommended Component Values”text changes. A new figure, Figure 10-1, follows Section “Recommended Component Values”

Change Bars

Change bars on subsequent ICS1893 data sheets indicate new documents posted to the web. Change bars within a new version of a document also indicates changes to the document.
Copyright 2000, Integrated Circuit Systems, Inc. All rights reserved.

June, 2000

ICS1893 - Release

Chapter 1 Abbreviations and Acronyms

Chapter 1 Abbreviations and Acronyms

Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet.

Table Abbreviations and Acronyms

Abbreviation / Acronym

Interpretation
4B/5B
4-Bit / 5-Bit Encoding/Decoding

ANSI

American National Standards Institute

CMOS
complimentary metal-oxide semiconductor

CSMA/CD

Carrier Sense Multiple Access with Collision Detection

Command Override Write
digital signal processing

End-of-Stream Delimiter

FDDI

Fiber Distributed Data Interface
frequency-locked loop

Fast Link Pulse

A ‘dead’time on the link following a 10Base-T packet, not to be confused with idle

International Electrotechnical Commission

IEEE

Institute of Electrical and Electronic Engineers

International Standards Organization

Latching High

Latching Low

Latching Maximum

Media Access Control

Max.
maximum

Mbps

Megabits per second

Media Dependent Interface

Management Frame

Media Independent Interface

Min.
Chapter 12 Ordering Information

NOTE EOL for non-green parts to occur on 5/13/10 per PDN U-09-01.
Figure 12-1 shows ordering information for the ICS1893 package:
• ICS1893Y-10 and ICS1893YI-10 industrial temp.
Figure ICS1893 Ordering Information

ICS 1893 Y -10
Chapter 12 Ordering Information

Package Type Y-10 = 10 x 10 TQFP Thin Quad Flat Pack

Device Identifier

Company Identifier Integrated Circuit Systems, Inc.

Copyright 2000, Integrated Circuit Systems, Inc. All rights reserved.

June, 2000

Integrated Circuit Systems, Inc.

Corporate Headquarters Silicon Valley Web Site:
2435 Boulevard of the Generals

P.O. Box 968

Valley Forge, PA 19482-0968

Telephone 610-630-5300

Fax:
610-630-5399
525 Race Street

San Jose, CA 95126-3448

Telephone 408-297-1201

Fax:
408-925-9460

Email:

ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ICS1893Y-10 Datasheet file may be downloaded here without warranties.

Datasheet ID: ICS1893Y-10 636955