DAC1653D1G0NLGA

DAC1653D1G0NLGA Datasheet

DAC1653D/DAC1658D

Part	Datasheet
DAC1653D1G0NLGA	DAC1653D1G0NLGA (pdf)

Related Parts	Information
DAC1658D1G25NLGA	DAC1658D1G25NLGA
DAC1653D1G5NLGA8	DAC1653D1G5NLGA8
DAC1653D1G5NLGA	DAC1653D1G5NLGA
DAC1658D1G5NLGA8	DAC1658D1G5NLGA8
DAC1658D2G0NLGA	DAC1658D2G0NLGA
DAC1658D1G0NLGA8	DAC1658D1G0NLGA8
DAC1658D2G0NLGA8	DAC1658D2G0NLGA8
DAC1653D2G0NLGA8	DAC1653D2G0NLGA8
DAC1658D1G5NLGA	DAC1658D1G5NLGA
DAC1653D1G0NLGA8	DAC1653D1G0NLGA8
DAC1658D1G25NLGA8	DAC1658D1G25NLGA8
DAC1653D2G0NLGA	DAC1653D2G0NLGA
DAC1658D1G0NLGA	DAC1658D1G0NLGA

PDF Datasheet Preview
DAC1653D/DAC1658D Dual 16-bit DAC 10 Gbps JESD204B interface x2, x4 and x8 interpolating Datasheet DAC1653D and DAC1658D are high-speed, high-performance 16-bit dual channel Digital-to-Analog Converters DACs . The devices provide sample rates up to 2 Gsps with selectable and interpolation filters optimized for multi-carrier and broadband wireless transmitters. When both devices are referred to in this data sheet, the following convention will be used DAC165xD. The DAC165xD integrates a JEDEC JESD204B compatible high-speed serial input data interface running up to 10 Gbps allowing dual channel input sampling at up to 1 Gsps over four differential lanes. It offers numerous advantages over traditional parallel digital interfaces: • Easier Printed-Circuit Board PCB layout • Lower radiated noise • Lower pin count • Self-synchronous link • Skew compensation • Deterministic latency • Multiple Device Synchronization MDS JESD204B subclass 1 compatible • Harmonic clocking support • Assured FPGA interoperability There are two versions of the DAC165xD: • Low common-mode output voltage part identification DAC1653D • High common-mode output voltage part identification DAC1658D An optional on-chip digital modulator converts the complex I/Q pattern from baseband to IF. The mixer frequency is set by writing to the Serial Peripheral Interface SPI control registers associated with the on-chip 40-bit Numerically Controlled Oscillator NCO . This accurately places the IF carrier in the frequency domain. The 13-bit phase adjustment feature, the 12-bit digital gain and the 16-bit digital offset enable full control of the analog output signals. The DAC165xD is fully compatible with device subclass 1 of the JEDEC JESD204B standard, guaranteeing deterministic and repeatable interface latency using the differential SYSREF signal. The device also supports harmonic clocking to reduce system-level clock synthesis and distribution challenges. Multiple Device Synchronization MDS enables multiple DAC channels to be sample synchronous and phase coherent to within one DAC clock period. MDS is ideal for LTE and LTE-A MIMO transceiver applications. The DAC165xD includes a or divider to achieve the best possible noise performance at the analog outputs, allowing harmonic clocking through the system. The internal regulator adjusts the full-scale output current between 10 mA and 30 mA. The device is available in a VFQFP-N 56 package 8 mm 8 mm . 2013, Integrated Device Technology, Inc. IDT and its subsidiaries reserves the right to change the detail specifications as may be required to permit improvements in the design of its product. DAC1653D/DAC1658D Dual 16-bit DAC 10 Gbps JESD204B interface x2, x4 and x8 interpolating Datasheet Dual channel 16-bit resolution GSps maximum output update rate JEDEC JESD204B device subclass I compatible: SFDRRBW = 88 dBc typical fs = Gsps interpolation bandwidth = 250 MHz fout = 150 MHz NSD = dBc/Hz typical fo = 70 MHz IMD3 = 85 dBc typical fs = Gsps interpolation SYSREF based deterministic and repeatable interface fo1 = 152 MHz fo2 = MHz latency Multiple device synchronization enables multiple DAC Four carriers ACLR = 76 dB typical fs = Gsps; channels to be sample synchronous and phase coherent fNCO = 350 MHz to within one DAC clock period 1, 2 or 4 configurable JESD204B serial input lanes RF enable/disable pin and RF automatic mute running up to 10 Gbps with embedded termination and programmable equalization gain CTLE 1 Gsps maximum baseband input data rate Clock divider by 2, 4, 6 and 8 available at the input of the clock path SPI interface 3-wire or 4-wire mode for control setting Group delay compensation and status monitoring Differential scalable output current from 10 mA to 30 mA Analog offset control 10-bit auxiliary DACs Embedded NCO with 40-bit programmable frequency Power-down mode controls and 16-bit phase adjustment Embedded complex IQ digital modulator ORDERING INFORMATION Datasheet Table Ordering information Type number Package Name DAC1653D2G0NLGA8 VFQFP-N 56 DAC1653D1G5NLGA8 VFQFP-N 56 DAC1653D1G0NLGA8 VFQFP-N 56 DAC1658D2G0NLGA8 VFQFP-N 56 DAC1658D1G5NLGA8 VFQFP-N 56 DAC1658D1G0NLGA8 VFQFP-N 56 DAC1653D2G0NLGA VFQFP-N 56 DAC1653D1G5NLGA VFQFP-N 56 DAC1653D1G0NLGA VFQFP-N 56 DAC1658D2G0NLGA VFQFP-N 56 DAC1658D1G5NLGA VFQFP-N 56 DAC1658D1G0NLGA VFQFP-N 56 Shipping Packaging VFQFP-N mm no lead Tape & Reel VFQFP-N mm no lead Tape & Reel VFQFP-N mm no lead Tape & Reel VFQFP-N mm no lead Tape & Reel VFQFP-N mm no lead Tape & Reel VFQFP-N mm no lead Tape & Reel If the physical lanes do not match with the ordering of the transmitter lanes, they can be reordered using the lane swapping module. As the DAC165xD allows various LMF configurations see Table 124 , it is important that the lane swapping respects the following reordering constraints linked to the L value see Table Table Logical lanes versus L values L value Logical lanes used for the Sample assembly module Binary Decimal logical lane 0 logical lane 1 logical lane 2 logical lane 3 logical lane 0 logical lane 2 logical lane 0 The selection of the logical lanes can be is specified by the LN_SEL_L_LNx bits of register LN_SEL see Table Table 34 shows the possible choices regarding the value of the L parameter. DAC1653D DAC1658D Datasheet IDT All rights reserved. 74 of 168 DAC1653D/DAC1658D Dual 16-bit DAC 10 Gbps JESD204B interface x2, x4 and x8 interpolating Datasheet Table Lane mapping between Logical and Physical lanes regarding the L value logical lane 0 physical lane 0 physical lane 0 physical lane 0 physical lane 1 physical lane 1 physical lane 1 physical lane 2 physical lane 2 physical lane 2 physical lane 3 physical lane 3 physical lane 3 logical lane 1 physical lane 0 not used not used physical lane 1 physical lane 2 Table Ordering information 3 Table Pin description 5 Table Limiting values 8 Table Thermal characteristics 9 Table Common characteristics 10 Table Currents characteristics 12 Table Specific characteristics 13 Table Dynamic characteristics DAC165xD 15 Table LMF configuration 26 Table Read mode or Write mode access description 28 Table Double buffered registers 29 Table SPI timing characteristics - 4 wires 31 Table SPI timing characteristics - 3 wires 32 Table Interpolation 35 Table 15 Interpolation filter coefficients 37 Table Complex modulator operation mode 38 Table Inversion filter coefficients 40 Table DAC transfer function 41 Table Mute event categories. 44 Table Mute rate availability 46 Table Digital offset adjustment 47 Table Level detector values 48 Table WCLK_DIV selection 52 Table CLKDIV_SEL_PHASE selection 52 Table Interpolation and CDI modes 53 Table Latency for LMF-S= without MDS , Phase correction, SSBM, and InvSin x/x 54 Table Additional latency 54 Table Auxiliary DAC transfer function 57 Table Relationship between various clocks 60 Table INTR_MOD settings 69 Table Logical lanes versus L values 73 Table Lane mapping between Logical and Physical lanes regarding the L value 74 Table Code group synchronization state machine 75 Table Sync_request control 75 Table SYNC output common mode voltage 76 Table SYNC output swing voltage 76 Table Counter source 80 Table HOLD_FLAG_CNT_EN options 80 Table Jitter tolerance scrambled pattern symbols sequence [1] 82 Table Definition of IO_SEL registers 83 Table Output signals for combination of indicators and ranges 84 Table Interface DAC DSP register allocation map 91 Table SPI configuration registers 92 Table Device power mode register 92 Table Chip type register 92 Table Chip registers 93 Table Chip vendor identification registers 93 Table SPI configuration register 93 Table Dual DAC core block register allocation map 94 Table Dual DAC core power configuration register 95 Table Word clock generation configuration register 95 Table High resolution auxiliary DAC register 96 Table Power On Clock Divider buffer configuration register 96 Table MDS SYSREF miscellaneous configuration register 96 Table Input clock divider register 96 Table Analog gain control registers 97 Table Auxiliary DACs registers 97 Table Main controls block register allocation map 99 Table Main controls register 100 Table Watch Dog control register 100 Table Power Down control register 100 Table EHS control register 101 Table EHS modes 101 Table Clock domain interface reset register 101 Table IO_MUX and MON_DCLK registers 101 Table Interface DAC DSP register allocation map 102 Table Transmission configuration register 104 Table Numerically controlled oscillator phase offset registers 104 Table Numerically controlled oscillator frequency registers 105 Table DAC output phase correction factor registers 105 Table DAC digital gain control registers 105 Table DAC output control register 106 Table Register level detector 106 Table DAC digital offset registers 106 Table Input word coding register 107 Table LSB/MSB of I/Q levels register 107 Table Signal power detector control register 108 Table SPD LSB/MSB registers 108 Table Mute, interrupt and temperature control register allocation map 109 Table Mute control registers 111 Table Mute alarm enable registers Table Mute rate control registers Table Mute wait period LSB/MSB registers Table IQ range limit LSB/MSB registers Table Interrupt control register Table Interrupt enable registers Table Interrupt flags registers Table Temperature Sensor control register Table Temperature Sensor level register Table Temperature Sensor clock divider register Table Temperature Sensor timer register Table Temperature Sensor output register Table Maximum temperature register Table Minimum temperature register Table DSP sample control register Table DSP read LSB/MSB registers Table Multiple Device Synchronization and Interrupt block register allocation map Table MDS main register 120 Table MDS IO control register 120 Table MDS manual adjustment delay register 121 Table MDS miscellaneous control register 121 Table MDS offset delay register 121 DAC1653D DAC1658D Datasheet IDT All rights reserved. 165 of 168 DAC1653D/DAC1658D Dual 16-bit DAC 10 Gbps JESD204B interface x2, x4 and x8 interpolating Table MDS window registers 122 Table LMFC period register 122 Table LMFC preset register 122 Table MDS adjustment delay register 122 Table MDS status registers 122 Table RX digital lane processing block register allocation map 124 Table Initial-lane alignment control register 126 Table Force alignment register 126 Table Synchronization output modes register 127 Table Physical lane polarity register 127 Table Physical lane selection register 128 Table Descrambler initialization values registers 128 Table Error handling register 129 Table Reinitialization control register 130 Table Miscellaneous control register 131 Table LMF control register 131 Table RX digital lane processing monitoring block register allocation map 132 Table Initial-lane alignment monitor registers 134 Table Initial-lane alignment buffer error register 134 Table Decoder flags register 135 Table Decoder /K/ symbols flag register 135 Table K28 flag registers 135 Table Decoder unexpected /K/ symbols flag register 137 Table Lock counter monitor registers 137 Table Lane code synchronization state register 138 Table Reset buffer error flags register 138 Table Miscellaneous interrupt enable register 138 Table LSB/MSB of flag_counter lane registers 139 Table Miscellaneous interrupt enable register 139 Table Miscellaneous interrupt enable register 140 Table Interrupt enable register 140 Table Flag counter control registers 141 Table Reset flags monitor register 141 Table Sample error rate interrupts control register 141 Table JESD204 receiver monitoring register allocation map 143 Table Sample rate error control registers 145 Table LSB/MSB of sample error rate counter registers 146 Table First JTSPAT with sample error rate registers 146 Table LSB/MSB of first sample error rate pattern registers 146 Table Multi-frame bytes registers 147 Table Force multi-frame bytes register 147 Table Overview of generic parts of register addresses 147 Table JESD204 read configuration block DAC X/Y lane 0/lane 1 register allocation map 148 Table Lane configuration registers 149 Table JESD204 read configuration block sample measurement registers 150 Table Lane 1/lane 0 sample LSB/MSB registers 151 Table Physical lane 1/lane 0 selection register 151 Table Lane 3/lane 2 sample LSB/MSB registers 151 Datasheet Table Physical lane 3/lane 2 selection register 152 Table RX physical layer control block register allocation map 153 Table High speed receiver clock data recovery divider register 154 Table High speed receiver equalizer control register 154 Table High speed equalizer gain registers 155 Table High speed receiver termination resistor voltage common-mode register 155 Table High speed resistor termination control register 155 Table Synchronization configuration control register 156 Table Synchronization test data control register 156 Table RX physical layer monitor register allocation map 157 Table Current high speed RX equalizer control DAC1653D DAC1658D Datasheet IDT All rights reserved. Ordering information 3 Block diagram 4 Pinning information 5 Pinning 5 Pin description. 5 Limiting values 8 Thermal characteristics 9 Static characteristics 10 Common characteristics 10 Specific characteristics 12 Dynamic characteristics. 15 Application information 25 General description 25 Device operation 27 SPI configuration block. 27 Protocol description 27 SPI controller configuration 28 Double buffering and Transfer mode 29 Device description 30 SPI RESET_N wait duration requirement 30 SPI timing description - 4 wires mode 30 SPI timing description - 3 wires mode 31 SPI IOs strength 32 Main device configuration and Start-up Sequence 33 Power Down mode 34 Interface DAC DSP block 35 Input data format 35 Finite Impulse Response FIR filters 35 Single Side Band Modulator SSBM . 38 40-bit NCO. 39 NCO low power 39 Minus 3dB 39 Phase correction. 39 Inverse sin x / x 40 Digital gain 40 Auto-mute 41 Digital offset adjustment. 47 Signal detectors. 48 Level detector 48 Signal Power Detector SPD 49

PDF Datasheet Preview

DAC1653D/DAC1658D

Dual 16-bit DAC 10 Gbps JESD204B interface x2, x4 and x8 interpolating

Datasheet

DAC1653D and DAC1658D are high-speed, high-performance 16-bit dual channel Digital-to-Analog Converters DACs . The devices provide sample rates up to 2 Gsps with selectable and interpolation filters optimized for multi-carrier and broadband wireless transmitters.

When both devices are referred to in this data sheet, the following convention will be used DAC165xD.

The DAC165xD integrates a JEDEC JESD204B compatible high-speed serial input data interface running up to 10 Gbps allowing dual channel input sampling at up to 1 Gsps over four differential lanes. It offers numerous advantages over traditional parallel digital interfaces:
• Easier Printed-Circuit Board PCB layout
• Lower radiated noise
• Lower pin count
• Self-synchronous link
• Skew compensation
• Deterministic latency
• Multiple Device Synchronization MDS JESD204B subclass 1 compatible
• Harmonic clocking support
• Assured FPGA interoperability

There are two versions of the DAC165xD:
• Low common-mode output voltage part identification DAC1653D
• High common-mode output voltage part identification DAC1658D

An optional on-chip digital modulator converts the complex I/Q pattern from baseband to IF. The mixer frequency is set by writing to the Serial Peripheral Interface SPI control registers associated with the on-chip 40-bit Numerically Controlled Oscillator NCO . This accurately places the IF carrier in the frequency domain. The 13-bit phase adjustment feature, the 12-bit digital gain and the 16-bit digital offset enable full control of the analog output signals.

The DAC165xD is fully compatible with device subclass 1 of the JEDEC JESD204B standard, guaranteeing deterministic and repeatable interface latency using the differential SYSREF signal. The device also supports harmonic clocking to reduce system-level clock synthesis and distribution challenges.

Multiple Device Synchronization MDS enables multiple DAC channels to be sample synchronous and phase coherent to within one DAC clock period. MDS is ideal for LTE and LTE-A MIMO transceiver applications.

The DAC165xD includes a or divider to achieve the best possible noise performance at the analog outputs, allowing harmonic clocking through the system. The internal regulator adjusts the full-scale output current between 10 mA and 30 mA.

The device is available in a VFQFP-N 56 package 8 mm 8 mm .
2013, Integrated Device Technology, Inc. IDT and its subsidiaries reserves the right to change the detail specifications as may be required to permit improvements in the design of its product.

DAC1653D/DAC1658D

Dual 16-bit DAC 10 Gbps JESD204B interface x2, x4 and x8 interpolating

Datasheet

Dual channel 16-bit resolution

GSps maximum output update rate JEDEC JESD204B device subclass I compatible:

SFDRRBW = 88 dBc typical fs = Gsps interpolation bandwidth = 250 MHz fout = 150 MHz

NSD = dBc/Hz typical fo = 70 MHz IMD3 = 85 dBc typical fs = Gsps interpolation

SYSREF based deterministic and repeatable interface
fo1 = 152 MHz fo2 = MHz
latency

Multiple device synchronization enables multiple DAC Four carriers ACLR = 76 dB typical fs = Gsps;
channels to be sample synchronous and phase coherent fNCO = 350 MHz
to within one DAC clock period
1, 2 or 4 configurable JESD204B serial input lanes

RF enable/disable pin and RF automatic mute
running up to 10 Gbps with embedded termination and
programmable equalization gain CTLE
1 Gsps maximum baseband input data rate

Clock divider by 2, 4, 6 and 8 available at the input of the
clock path

SPI interface 3-wire or 4-wire mode for control setting Group delay compensation
and status monitoring

Differential scalable output current from 10 mA to 30 mA Analog offset control 10-bit auxiliary DACs

Embedded NCO with 40-bit programmable frequency Power-down mode controls
and 16-bit phase adjustment

Embedded complex IQ digital modulator
ORDERING INFORMATION

Datasheet
Table Ordering information

Type number

Package

Name

DAC1653D2G0NLGA8

VFQFP-N 56

DAC1653D1G5NLGA8

VFQFP-N 56

DAC1653D1G0NLGA8

VFQFP-N 56

DAC1658D2G0NLGA8

VFQFP-N 56

DAC1658D1G5NLGA8

VFQFP-N 56

DAC1658D1G0NLGA8

VFQFP-N 56

DAC1653D2G0NLGA

VFQFP-N 56

DAC1653D1G5NLGA

VFQFP-N 56

DAC1653D1G0NLGA

VFQFP-N 56

DAC1658D2G0NLGA

VFQFP-N 56

DAC1658D1G5NLGA

VFQFP-N 56

DAC1658D1G0NLGA

VFQFP-N 56

Shipping Packaging

VFQFP-N mm no lead

Tape & Reel

VFQFP-N mm no lead

Tape & Reel

VFQFP-N mm no lead

Tape & Reel

VFQFP-N mm no lead

Tape & Reel

VFQFP-N mm no lead

Tape & Reel

VFQFP-N mm no lead

Tape & Reel
If the physical lanes do not match with the ordering of the transmitter lanes, they can be reordered using the lane swapping module. As the DAC165xD allows various LMF configurations see Table 124 , it is important that the lane swapping respects the following reordering constraints linked to the L value see Table

Table Logical lanes versus L values

L value

Logical lanes used for the Sample assembly module

Binary Decimal
logical lane 0
logical lane 1
logical lane 2
logical lane 3
logical lane 0
logical lane 2
logical lane 0

The selection of the logical lanes can be is specified by the LN_SEL_L_LNx bits of register LN_SEL see Table

Table 34 shows the possible choices regarding the value of the L parameter.

DAC1653D DAC1658D

Datasheet

IDT All rights reserved.
74 of 168

DAC1653D/DAC1658D

Dual 16-bit DAC 10 Gbps JESD204B interface x2, x4 and x8 interpolating

Datasheet

Table Lane mapping between Logical and Physical lanes regarding the L value
logical lane 0
physical lane 0
physical lane 0
physical lane 0
physical lane 1
physical lane 1
physical lane 1
physical lane 2
physical lane 2
physical lane 2
physical lane 3
physical lane 3
physical lane 3
logical lane 1
physical lane 0
not used
not used
physical lane 1
physical lane 2
Table Ordering information 3 Table Pin description 5 Table Limiting values 8 Table Thermal characteristics 9 Table Common characteristics 10 Table Currents characteristics 12 Table Specific characteristics 13 Table Dynamic characteristics DAC165xD 15 Table LMF configuration 26 Table Read mode or Write mode access description 28 Table Double buffered registers 29 Table SPI timing characteristics - 4 wires 31 Table SPI timing characteristics - 3 wires 32 Table Interpolation 35 Table 15 Interpolation filter coefficients 37 Table Complex modulator operation mode 38 Table Inversion filter coefficients 40 Table DAC transfer function 41 Table Mute event categories. 44 Table Mute rate availability 46 Table Digital offset adjustment 47 Table Level detector values 48 Table WCLK_DIV selection 52 Table CLKDIV_SEL_PHASE selection 52 Table Interpolation and CDI modes 53 Table Latency for LMF-S= without MDS , Phase
correction, SSBM, and InvSin x/x 54 Table Additional latency 54 Table Auxiliary DAC transfer function 57 Table Relationship between various clocks 60 Table INTR_MOD settings 69 Table Logical lanes versus L values 73 Table Lane mapping between Logical and Physical
lanes regarding the L value 74 Table Code group synchronization state machine 75 Table Sync_request control 75 Table SYNC output common mode voltage 76 Table SYNC output swing voltage 76 Table Counter source 80 Table HOLD_FLAG_CNT_EN options 80 Table Jitter tolerance scrambled pattern symbols
sequence [1] 82 Table Definition of IO_SEL registers 83 Table Output signals for combination of indicators
and ranges 84 Table Interface DAC DSP register allocation map 91 Table SPI configuration registers 92 Table Device power mode register 92 Table Chip type register 92 Table Chip registers 93 Table Chip vendor identification registers 93 Table SPI configuration register 93 Table Dual DAC core block register allocation map 94 Table Dual DAC core power configuration register 95 Table Word clock generation configuration register 95 Table High resolution auxiliary DAC register 96

Table Power On Clock Divider buffer configuration register 96

Table MDS SYSREF miscellaneous configuration register 96

Table Input clock divider register 96 Table Analog gain control registers 97 Table Auxiliary DACs registers 97 Table Main controls block register allocation map 99 Table Main controls register 100 Table Watch Dog control register 100 Table Power Down control register 100 Table EHS control register 101 Table EHS modes 101 Table Clock domain interface reset register 101 Table IO_MUX and MON_DCLK registers 101 Table Interface DAC DSP register allocation map 102 Table Transmission configuration register 104 Table Numerically controlled oscillator phase offset
registers 104 Table Numerically controlled oscillator frequency
registers 105 Table DAC output phase correction factor registers 105 Table DAC digital gain control registers 105 Table DAC output control register 106 Table Register level detector 106 Table DAC digital offset registers 106 Table Input word coding register 107 Table LSB/MSB of I/Q levels register 107 Table Signal power detector control register 108 Table SPD LSB/MSB registers 108 Table Mute, interrupt and temperature control
register allocation map 109 Table Mute control registers 111 Table Mute alarm enable registers Table Mute rate control registers Table Mute wait period LSB/MSB registers Table IQ range limit LSB/MSB registers Table Interrupt control register Table Interrupt enable registers Table Interrupt flags registers Table Temperature Sensor control register Table Temperature Sensor level register Table Temperature Sensor clock divider register Table Temperature Sensor timer register Table Temperature Sensor output register Table Maximum temperature register Table Minimum temperature register Table DSP sample control register Table DSP read LSB/MSB registers Table Multiple Device Synchronization and

Interrupt block register allocation map Table MDS main register 120 Table MDS IO control register 120 Table MDS manual adjustment delay register 121 Table MDS miscellaneous control register 121 Table MDS offset delay register 121

DAC1653D DAC1658D

Datasheet

IDT All rights reserved.
165 of 168

DAC1653D/DAC1658D

Dual 16-bit DAC 10 Gbps JESD204B interface x2, x4 and x8 interpolating

Table MDS window registers 122 Table LMFC period register 122 Table LMFC preset register 122 Table MDS adjustment delay register 122 Table MDS status registers 122 Table RX digital lane processing block register
allocation map 124 Table Initial-lane alignment control register 126 Table Force alignment register 126 Table Synchronization output modes register 127 Table Physical lane polarity register 127 Table Physical lane selection register 128 Table Descrambler initialization values registers 128 Table Error handling register 129 Table Reinitialization control register 130 Table Miscellaneous control register 131 Table LMF control register 131 Table RX digital lane processing monitoring block
register allocation map 132 Table Initial-lane alignment monitor registers 134 Table Initial-lane alignment buffer error register 134 Table Decoder flags register 135 Table Decoder /K/ symbols flag register 135 Table K28 flag registers 135 Table Decoder unexpected /K/ symbols flag
register 137 Table Lock counter monitor registers 137 Table Lane code synchronization state register 138 Table Reset buffer error flags register 138 Table Miscellaneous interrupt enable register 138 Table LSB/MSB of flag_counter lane registers 139 Table Miscellaneous interrupt enable register 139 Table Miscellaneous interrupt enable register 140 Table Interrupt enable register 140 Table Flag counter control registers 141 Table Reset flags monitor register 141 Table Sample error rate interrupts control register 141 Table JESD204 receiver monitoring register
allocation map 143 Table Sample rate error control registers 145 Table LSB/MSB of sample error rate counter
registers 146 Table First JTSPAT with sample error rate
registers 146 Table LSB/MSB of first sample error rate pattern
registers 146 Table Multi-frame bytes registers 147 Table Force multi-frame bytes register 147 Table Overview of generic parts of register
addresses 147 Table JESD204 read configuration block DAC X/Y
lane 0/lane 1 register allocation map 148 Table Lane configuration registers 149 Table JESD204 read configuration block sample
measurement registers 150 Table Lane 1/lane 0 sample LSB/MSB registers 151 Table Physical lane 1/lane 0 selection register 151 Table Lane 3/lane 2 sample LSB/MSB registers 151

Datasheet

Table Physical lane 3/lane 2 selection register 152 Table RX physical layer control block register
allocation map 153 Table High speed receiver clock data recovery
divider register 154 Table High speed receiver equalizer control
register 154 Table High speed equalizer gain registers 155 Table High speed receiver termination resistor
voltage common-mode register 155 Table High speed resistor termination control
register 155 Table Synchronization configuration control
register 156 Table Synchronization test data control register 156 Table RX physical layer monitor register allocation
map 157 Table Current high speed RX equalizer control

DAC1653D DAC1658D

Datasheet

IDT All rights reserved.
Ordering information 3

Block diagram 4

Pinning information 5

Pinning 5

Pin description. 5

Limiting values 8

Thermal characteristics 9

Static characteristics 10

Common characteristics 10

Specific characteristics 12

Dynamic characteristics. 15

Application information 25

General description 25

Device operation 27

SPI configuration block. 27

Protocol description 27

SPI controller configuration 28

Double buffering and Transfer mode 29

Device description 30

SPI RESET_N wait duration requirement 30

SPI timing description - 4 wires mode 30

SPI timing description - 3 wires mode 31

SPI IOs strength 32

Main device configuration and Start-up

Sequence 33

Power Down mode 34

Interface DAC DSP block 35

Input data format 35

Finite Impulse Response FIR filters 35

Single Side Band Modulator SSBM . 38
40-bit NCO. 39

NCO low power 39

Minus 3dB 39

Phase correction. 39

Inverse sin x / x 40

Digital gain 40

Auto-mute 41

Digital offset adjustment. 47

Signal detectors. 48

Level detector 48

Signal Power Detector SPD 49

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Datasheet ID: DAC1653D1G0NLGA 636941