ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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ICS9173-01CS08LFT (pdf) |
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Integrated Circuit Systems, Inc. AV 9173 - 01 Video Genlock PLL The AV9173-01 provides the analog circuit blocks required for implementing a video genlock dot pixel clock generator. It contains a phase detector, charge pump, loop filter, and voltage-controlled oscillator VCO . By grouping these critical analog blocks into one IC and utilizing external digital functions, performance and design flexibility are optimized as are development time and system cost. When used with an external clock divider, the AV9173-01 forms a Phase-Locked Loop configured as a frequency synthesizer. The AV9173-01 is designed to accept video horizontal synchronization h-sync pulses and produce a video dot clock. A separated, negative-going sync input reference pulse is required at pin 2 IN . The AV9173-01 is also suited for other clock recovery applications in such areas as data communications. • Phase-detector/VCO circuit block • Ideal for genlock system • Reference clock range 25 kHz to 1MHz for full output clock range • Input clocks down to 12 kHz possible with restricted output conditions see Table 1 • Output clock range to 75 MHz • On-chip loop filter • Single 5 volt power supply • Low power CMOS technology • Small 8-pin DIP or SOIC package Block Diagram ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. AV9173- 01 Pin Configuration 8-Pin DIP or SOIC Pin Descriptions PIN NUMBE- R 1 2 3 4 5 6 PIN NAME FBIN IN GND FS0 OE CLK1 VDD CLK2 TYPE Input Input Output Output Feedback Input for reference sync pulse Ground Frequency Select 0 input Output Enable Clock Output 1 Power Supply +5V Clock Output 2 Divided-by-2 from Clock 1 Table 1 Allowable Input Frequency to Output Frequency Outputs in MHz fIN kHz 12 fIN 14 kHz 14 < fIN 17 kHz 17 < fIN 30 kHz 30 < fIN 35 kHz 35 < fIN 1000 kHz fOUT for FS = 0 MHz CLK1 Output CLK2 Output to 75 to 75 to 75 to 75 to 75 fOUT for FS = 1 MHz CLK1 Output CLK2 Output AV9173- 01 Using the AV9173-01 Most video sources, such as video cameras, are asynchronous, free-running devices. To digitize video or synchronize one video source to another free-running reference video source, a video “genlock” generator lock circuit is required. The AV9173-01 integrates the analog blocks which make the task much easier. 8-Pin SOIC PACKAGE Ordering Information AV9173-01CN08LF - or - AV9173-01CS08LF Example: XXX XXXX - PPP M X#Wl LF RoHS Compliant Optional Lead Count & Package Width Lead Count = 1, 2 or 3 digits W = SOIC or DIP None = Standard Width Package Type N = DIP Plastic S = SOIC Pattern Number 2 or 3 digit number for parts with ROM code patterns Device Type consists of 3 or 4 digit numbers Prefix ICS, AV = Standard Device ICS reserves the right to make changes in the device data identified in this 6 publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. 6/21/2005 1.Added LF Ordering Information. AV9173- 01 Page # 6 |
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