8V19N407Z-24NLGI

8V19N407Z-24NLGI Datasheet

8V19N408

Part	Datasheet
8V19N407Z-24NLGI	8V19N407Z-24NLGI (pdf)

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NG Jitter Attenuator and Clock Synthesizer 8V19N408 DATA SHEET 8V19N408 is a fully integrated NG Jitter Attenuator and Clock Synthesizer. The device is a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards and is optimized to deliver excellent phase noise performance. The device supports JESD204B subclass 0 and 1 clock implementations. The device is very flexible in programming of the output frequency and phase. A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for best possible phase noise characteristics.The second stage PLL lock on the VCXO-PLL output signal and synthesizes the target frequency. For flexibility, the second-stage PLL can use one of two VCOs at 2400MHz - 2500MHz VCO-0 and 2920MHz - 3000MHz VCO-1 . The device supports the clock generation of high-frequency clocks from the selected VCO and low-frequency system reference signals SYSREF . The system reference signals are internally synchronized to the clock signals. Delay functions exist for achieving alignment and controlled phase delay between system reference and clock signals and to align/delay individual output signals. The input is monitored for activity. Short-term hold-over is provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers and phase adjustment capabilities are added for flexibility. The device is configured through a 4-wire SP serial interface and reports lock and signal loss status in internal registers and optionally via lock detect nINT output. The device is packaged in a lead-free RoHS 6 72-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. The device is a member of the high-performance clock family from IDT. • Core timing unit for JESD204B wireless infrastructure clocks • Fourth generation NG technology • First stage PLL uses an external VCXO for jitter attenuation • Second PLL stage facilitates a dual integrated VCO for flexible frequency synthesis • Integrated VCO frequencies 2400MHz - 2500MHz VCO-0 and 2920MHz - 3000MHz VCO-1 • Five differential configurable LVPECL, LVDS clock outputs with a variable output amplitude • Four differential LVDS system reference SYSREF signal outputs • Synchronization between clock and system reference signals • Wide input frequency range supported by 8-bit pre- and 15-bit VCOX-PLL feedback divider • Output clock frequencies 2457.6MHz ÷N VCO-0 and 2949.12MHz ÷N VCO-1 in wireless infrastructure applications • Three independent output clock frequency dividers N range of ÷1 to ÷96 • Clock output frequency range VC0-0 2400MHz - 2500MHz ÷N • Clock output frequency range VC0-1 2920MHz - 3000MHz ÷N • Phase delay capabilities for alignment/delay for clock and SYSREF signals • Individual output phase adjustment Clock one-period of the selected VCO frequency in 64 steps • Individual output phase adjustment SYSREF approximately half-period of the selected VCO frequency in 8 steps • Internal, SPI controlled SYSREF pulse generation • SYSREF frequencies fVCO ÷ NS 10 dividers • NS divider range ÷64 to ÷2048 • SYSREF wireless infrastructure 1.2MHz 46.08MHz • Clock input compatible with LVPECL, LVDS, LVCMOS signals • Dedicated power-down features for reducing power consumption • Input clock monitoring • Holdover for temporary loss of input signal scenarios • Support of output power-down and output disable • Typical clock output phase noise at 1228.8MHz: 1kHz offset dBc/Hz 10kHz offset dBc/Hz 100kHz offset dBc/Hz 1MHz offset dBc/Hz 10MHz offset dBc/Hz • RMS phase noise 12kHz 20MHz <100fs target • Status conditions with programmable functionality for loss-of-lock and loss-of-reference indication • Lock detect nINT output for status change indication • LVCMOS/LVTTL compatible SPI serial interface • 3.3V core and output supply mode • Control pins support 3.3V I/O logic levels: SPI interface levels support selectable 3.3V/1.8V logic levels • -40°C to +85°C ambient operating temperature • Lead-free RoHS 6 72-lead VFQFN packaging 2015 INTEGRATED DEVICE TECHNOLOGY, INC. 8V19N408 DATA SHEET Block Diagram CV0 CV1 RV fVCXO nVCXO VCXO C01 C02 R0 VCO0R VCO0 LF0 LF1 VCO1 VCO1R C12 C11 R1 CLK nCLK VCXO-PLL Ordering Information Table Ordering Information Part/Order Number 8V19N408ZNLGI 8V19N408ZNLGI8 Marking IDT8V9N408ZNLGI Package 72 Lead VFQFN, Lead-Free 72 Lead VFQFN, Lead-Free Shipping Packaging Tray Tape & Reel Temperature -40C to 85C -40C to 85C NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER Page 29 Description of Change AC Characteristics Table - typographical spec errors for VO pp  LVPECL Output Voltage Swing  400mV Amplitude Setting minimum and maximum specs; LVPECL Differential Output Voltage Swing  400mV Amplitude Setting minimum, typical and maximum specs 1000mV Amplitude Setting typical spec 8V19N408 DATA SHEET Date 10/1/15 NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 USA Sales 1-800-345-7015 or 408-284-8200 Fax 408-284-2775 Tech Support email: DISCLAIMER Integrated Device Technology, Inc. IDT and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology IDT assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2015 Integrated Device Technology, Inc. All rights reserved.

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NG Jitter Attenuator and Clock Synthesizer
8V19N408

DATA SHEET
8V19N408 is a fully integrated NG Jitter Attenuator and Clock Synthesizer. The device is a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards and is optimized to deliver excellent phase noise performance. The device supports JESD204B subclass 0 and 1 clock implementations. The device is very flexible in programming of the output frequency and phase. A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for best possible phase noise characteristics.The second stage PLL lock on the VCXO-PLL output signal and synthesizes the target frequency. For flexibility, the second-stage PLL can use one of two VCOs at 2400MHz - 2500MHz VCO-0 and 2920MHz - 3000MHz VCO-1 .

The device supports the clock generation of high-frequency clocks from the selected VCO and low-frequency system reference signals SYSREF . The system reference signals are internally synchronized to the clock signals. Delay functions exist for achieving alignment and controlled phase delay between system reference and clock signals and to align/delay individual output signals. The input is monitored for activity. Short-term hold-over is provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers and phase adjustment capabilities are added for flexibility. The device is configured through a 4-wire SP serial interface and reports lock and signal loss status in internal registers and optionally via lock detect nINT output. The device is packaged in a lead-free RoHS 6 72-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. The device is a member of the high-performance clock family from IDT.
• Core timing unit for JESD204B wireless infrastructure clocks
• Fourth generation NG technology
• First stage PLL uses an external VCXO for jitter attenuation
• Second PLL stage facilitates a dual integrated VCO for flexible
frequency synthesis
• Integrated VCO frequencies 2400MHz - 2500MHz VCO-0 and
2920MHz - 3000MHz VCO-1
• Five differential configurable LVPECL, LVDS clock outputs with a
variable output amplitude
• Four differential LVDS system reference SYSREF signal outputs
• Synchronization between clock and system reference signals
• Wide input frequency range supported by 8-bit pre- and 15-bit

VCOX-PLL feedback divider
• Output clock frequencies 2457.6MHz ÷N VCO-0 and
2949.12MHz ÷N VCO-1 in wireless infrastructure applications
• Three independent output clock frequency dividers N range of ÷1
to ÷96
• Clock output frequency range VC0-0 2400MHz - 2500MHz ÷N
• Clock output frequency range VC0-1 2920MHz - 3000MHz ÷N
• Phase delay capabilities for alignment/delay for clock and

SYSREF signals
• Individual output phase adjustment Clock one-period of the
selected VCO frequency in 64 steps
• Individual output phase adjustment SYSREF approximately
half-period of the selected VCO frequency in 8 steps
• Internal, SPI controlled SYSREF pulse generation
• SYSREF frequencies fVCO ÷ NS 10 dividers
• NS divider range ÷64 to ÷2048
• SYSREF wireless infrastructure 1.2MHz 46.08MHz
• Clock input compatible with LVPECL, LVDS, LVCMOS signals
• Dedicated power-down features for reducing power consumption
• Input clock monitoring
• Holdover for temporary loss of input signal scenarios
• Support of output power-down and output disable
• Typical clock output phase noise at 1228.8MHz:
1kHz offset dBc/Hz 10kHz offset dBc/Hz 100kHz offset dBc/Hz 1MHz offset dBc/Hz 10MHz offset dBc/Hz
• RMS phase noise 12kHz 20MHz <100fs target
• Status conditions with programmable functionality for loss-of-lock
and loss-of-reference indication
• Lock detect nINT output for status change indication
• LVCMOS/LVTTL compatible SPI serial interface
• 3.3V core and output supply mode
• Control pins support 3.3V I/O logic levels:

SPI interface levels support selectable 3.3V/1.8V logic levels
• -40°C to +85°C ambient operating temperature
• Lead-free RoHS 6 72-lead VFQFN packaging
2015 INTEGRATED DEVICE TECHNOLOGY, INC.
8V19N408 DATA SHEET

Block Diagram

CV0 CV1 RV
fVCXO
nVCXO VCXO

C01 C02 R0

VCO0R VCO0 LF0 LF1 VCO1 VCO1R

C12 C11 R1

CLK nCLK

VCXO-PLL
Ordering Information
Table Ordering Information

Part/Order Number 8V19N408ZNLGI 8V19N408ZNLGI8

Marking IDT8V9N408ZNLGI

Package 72 Lead VFQFN, Lead-Free 72 Lead VFQFN, Lead-Free

Shipping Packaging

Tray

Tape & Reel

Temperature -40C to 85C -40C to 85C

NG JITTER ATTENUATOR AND

CLOCK SYNTHESIZER

Page 29

Description of Change

AC Characteristics Table - typographical spec errors for VO pp  LVPECL Output Voltage Swing  400mV Amplitude Setting minimum and maximum specs; LVPECL Differential Output Voltage Swing  400mV Amplitude Setting minimum, typical and maximum specs 1000mV Amplitude Setting typical spec
8V19N408 DATA SHEET Date
10/1/15

NG JITTER ATTENUATOR AND

CLOCK SYNTHESIZER

Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 USA

Sales 1-800-345-7015 or 408-284-8200 Fax 408-284-2775

Tech Support email:

DISCLAIMER Integrated Device Technology, Inc. IDT and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology IDT assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners.

Copyright 2015 Integrated Device Technology, Inc. All rights reserved.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 8V19N407Z-24NLGI Datasheet file may be downloaded here without warranties.

Datasheet ID: 8V19N407Z-24NLGI 636750