IDT79RC32V364-133DAG

IDT79RC32V364-133DAG Datasheet

x High-performance embedded RISControllerTM microprocessor, based on IDT RISCore32300TM 32-bit CPU core Based on MIPS 32 RISC architecture with enhancements Scalar 5-stage pipeline minimizes branch and load delays 66 Million multiply accumulate MAC Mul-Add/second 133MHz 100 and 133 frequencies

Part	Datasheet
IDT79RC32V364-133DAG	IDT79RC32V364-133DAG (pdf)

Related Parts	Information
IDT79RC32V364-100DA	IDT79RC32V364-100DA
IDT79RC32V364-133DA	IDT79RC32V364-133DA
IDT79RC32V364-100DAG	IDT79RC32V364-100DAG

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RISControllerTM Embedded 32-bit Microprocessor, based on RISCore32300 79RC32364 x High-performance embedded RISControllerTM microprocessor, based on IDT RISCore32300TM 32-bit CPU core Based on MIPS 32 RISC architecture with enhancements Scalar 5-stage pipeline minimizes branch and load delays 66 Million multiply accumulate MAC Mul-Add/second 133MHz 100 and 133 frequencies x MIPS 32 ISA instruction set architecture MIPS IV compatible conditional move instructions MIPS IV superset PREF prefetch instruction Fast multiplier with atomic multiply-add, multiply-sub Count leading zeros/ones instructions x Large, efficient on-chip caches Separate 8kB Instruction cache and 2kB Data cache 2-way set associative Write-back and write-through support on a per page basis Optional cache locking with “per line” resolution, to facilitate deterministic response Simultaneous instruction and data fetch in each clock cycle, sustained rate, achieves over 1 GB/sec bandwidth x Flexible RC4000 compatible MMU with 32-page TLB on-chip Variable page size Variable number of locked entries No performance penalty for address translation x Flexible bus interface allows simple, low-cost designs Bus interface runs at a fraction of pipeline rate Programmable port-width interface 8-,16-, 32-bit memory and I/O regions Programmable bus turnaround times BTA Supports single data or burst transactions x Improved real-time support Fast interrupt decode x Low-power operation Active power management powers down inactive units Typical power 700mW 133MHz Stand-by mode <300mW x Enhanced JTAG interface, for low-cost in-circuit emulation ICE x MIPS architecture ensures applications software compatibility throughout the RISController series of embedded processors x Industrial temperature range support x 3.3V operation core and I/O Block Diagram RISCore32300TM Extended MIPS 32 Integer CPU Core MMU RISCore4000 Compatible w/ System Control TLB Coprocessor CPO Enhanced JTAG ICE Interface 8kB I-Cache, 2-set, lockable 2kB D-Cache, 2-set, lockable, write-back/write-through Clock Generation Unit RISCore32300 Internal Bus Interface RC32364 Bus Interface Unit The IDT logo is a trademark and ORION, RC4650, RC4640, RV4640, RC4600, RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc. 2000 Integrated Device Technology, Inc. 1 of 21 Notice The information in this document is subject to change without notice June 20, 2000 DSC 4510 79RC32364 Device Overview Targeted to a variety of performance-hungry, cost-sensitive embedded applications, the RC32364 is a new low-powered, low-cost member of the Integrated Device Technology, Inc. IDT RISController Series of Embedded Microprocessors. The RC32364 brings 64-bit performance levels to lower cost systems. High performance is achieved through the use of advanced techniques such as large on-chip two-way set-associative caches, a streamlined high-speed pipeline, high-bandwidth, and facilities such as early restart for data cache misses. Also, through IDT proprietary enhancements to the base MIPS architecture, the processor’s performance, in particular applications, is further extended. The RC32364 is the first member of a new processor family that uses IDT’s proprietary RISCore32300 CPU core. The RISCore32300 core continues IDT’s tradition of high-performance through high-speed pipelines, high-bandwidth caches, and architectural extensions that serve the needs of specific markets yet the RC32364 provides these capabilities in a low-cost, high-speed 32-bit enhanced MIPS architecture core, enabling a new level of price performance. Around the RISCore32300, the RC32364 integrates a fully RC5000 compatible memory management unit MMU , substantial amounts of efficient cache memory, an enhanced debug capability, digital signal processing DSP extensions, and a low-cost system interface. The resulting device is well suited to the needs of mid-range communications equipment, xDSL equipment, and consumer devices. Also, being upwardly software compatible with the RC3000 family, the RC32364 will serve in many of the same applications as well as support applications that require integer DSP functions. Device Performance RC32364 is rated at 175 dhrystone MIPS at 133MHz. The internal cache bandwidth is over GB/sec, with external bus bandwidth of 260MB/sec. Computational performance is further enhanced by the device’s DSP capability, which supports 66 Million multiply-accummulate MAC operations per second at 133MHz. The RISCore32300 uses a 5-stage pipeline, similar to the RISCore3000 and the RISCore4000 processor families. The simplicity of the pipeline enables the processor to achieve high frequency while minimizing device complexity, reducing both cost and power consumption. Because this pipeline is not sensitive to the data conflicts that slowdown super-scalar machines, an added benefit to this pipeline approach is that sustained actual performance is much closer to the theoretical maximum performance. The RISCore32300 integer execution unit implements the MIPS 32 ISA. The RISCore32300 thus implements a load/store architecture with single-cycle ALU operations logical, shift, add, subtract and an autonomous multiply/divide unit. The 32-bit register resources include 32 general-purpose orthogonal integer registers, the HI/LO result register for the integer multiply/divide unit, and the program counter. RISCore32300 CPU core features include: x MIPS IV prefetch operations, with various innovative hint subfields High-order multiplexed address and data bits. Regardless of system byte ordering, AD 31 is the MSB of the address. AD 3:0 Size 3:0 /Data 3:0 Valid sizes for the RC32364 are as follows: Addr 3:2 ADS Size 3 Size 2 Size 1 Size 0 0 1 0 1 0 Transfer Width 16 bytes 1 byte 2 bytes 3 bytes 4 bytes Other encodings allow future generations to service other transfer sizes. During the data phase, AD[3:0] represents the Data 3:0 . Addr 3:2 Non-multiplexed address lines. These serve as the word within block address for cache refills Addr 3:2 . The word within block address bits count in a sub-block ordering. Address Latch Enable. This signal provides set-up and hold times around the address phase of the AD bus. Address Strobe This active-low signal indicates valid address and the start of a new bus transaction. The processor asserts ADS* for the entire address cycle. This is the inverse of the ALE signal. Table 3 System Interface Pin Descriptions Page 1 of 4 6 of 21 Notice The information in this document is subject to change without notice June 20, 2000 79RC32364 Pin Width 1:0 Type Bus Width Indicates the Physical Memory/IO data bus size as follows: Width 1 Width 0 0 1 0 1 Port Width 8 bits 16 bits 32 bits Reserved BE 3:0 ByteEnables 3:0 /Addr 1:0 Indicates which byte lanes are expected to participate in the transfer. Port Width 32-bit 16-bit 8-bit Byte Lanes Enabled In Data Transfer Used Used Used Used Byte High Enable Not Used Address Bit 1 Byte Low Enable Not Used Not Used Address Bit 1 Address Bit 0 Driven High Driven High A1 CIP* I/D* DataEn* DT/R* Ack* Last* Handshake Interface Ordering Information IDT79RCXX YY Product Type Operating Voltage XXXX Device Type 999 Speed A Package A Temp range/ Process Blank Commercial Temperature Range 0°C to +85°C Case Industrial Temperature Range -40°C to +85°C Case DA 144-pin TQFP 100 MHz PClk 133 MHz PClk 364 Embedded Processor 3.3V +/-5% 79RC32 32-bit Embedded Microprocessor Valid Combinations IDT79RC32V364 - 100,133 DA IDT79RC32V364 - 100,133 DAI TQFP package, Commercial Temperature TQFP package, Industrial Temperature CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775 The IDT logo is a trademark of Integrated Device Technology, Inc. 21 of 21 *Notice The information in this document is subject to change without notice for Tech Support email phone 408-284-8208 June 20, 2000

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RISControllerTM Embedded 32-bit Microprocessor, based on RISCore32300
79RC32364
x High-performance embedded RISControllerTM microprocessor, based on IDT RISCore32300TM 32-bit CPU core Based on MIPS 32 RISC architecture with enhancements Scalar 5-stage pipeline minimizes branch and load delays 66 Million multiply accumulate MAC Mul-Add/second 133MHz 100 and 133 frequencies
x MIPS 32 ISA instruction set architecture MIPS IV compatible conditional move instructions MIPS IV superset PREF prefetch instruction Fast multiplier with atomic multiply-add, multiply-sub Count leading zeros/ones instructions
x Large, efficient on-chip caches Separate 8kB Instruction cache and 2kB Data cache 2-way set associative Write-back and write-through support on a per page basis Optional cache locking with “per line” resolution, to facilitate deterministic response Simultaneous instruction and data fetch in each clock cycle, sustained rate, achieves over 1 GB/sec bandwidth
x Flexible RC4000 compatible MMU with 32-page TLB on-chip Variable page size Variable number of locked entries No performance penalty for address translation
x Flexible bus interface allows simple, low-cost designs Bus interface runs at a fraction of pipeline rate Programmable port-width interface 8-,16-, 32-bit memory and I/O regions Programmable bus turnaround times BTA Supports single data or burst transactions
x Improved real-time support Fast interrupt decode
x Low-power operation Active power management powers down inactive units Typical power 700mW 133MHz Stand-by mode <300mW
x Enhanced JTAG interface, for low-cost in-circuit emulation ICE
x MIPS architecture ensures applications software compatibility throughout the RISController series of embedded processors
x Industrial temperature range support
x 3.3V operation core and I/O

Block Diagram

RISCore32300TM Extended MIPS 32 Integer CPU Core

MMU RISCore4000 Compatible w/ System Control

TLB Coprocessor CPO

Enhanced JTAG ICE Interface
8kB I-Cache, 2-set, lockable
2kB D-Cache, 2-set, lockable, write-back/write-through

Clock Generation

Unit

RISCore32300 Internal Bus Interface RC32364 Bus Interface Unit

The IDT logo is a trademark and ORION, RC4650, RC4640, RV4640, RC4600, RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
2000 Integrated Device Technology, Inc.
1 of 21
*Notice The information in this document is subject to change without notice

June 20, 2000

DSC 4510
79RC32364

Device Overview

Targeted to a variety of performance-hungry, cost-sensitive embedded applications, the RC32364 is a new low-powered, low-cost member of the Integrated Device Technology, Inc. IDT RISController Series of Embedded Microprocessors.

The RC32364 brings 64-bit performance levels to lower cost systems. High performance is achieved through the use of advanced techniques such as large on-chip two-way set-associative caches, a streamlined high-speed pipeline, high-bandwidth, and facilities such as early restart for data cache misses. Also, through IDT proprietary enhancements to the base MIPS architecture, the processor’s performance, in particular applications, is further extended.

The RC32364 is the first member of a new processor family that uses IDT’s proprietary RISCore32300 CPU core. The RISCore32300 core continues IDT’s tradition of high-performance through high-speed pipelines, high-bandwidth caches, and architectural extensions that serve the needs of specific markets yet the RC32364 provides these capabilities in a low-cost, high-speed 32-bit enhanced MIPS architecture core, enabling a new level of price performance.

Around the RISCore32300, the RC32364 integrates a fully RC5000 compatible memory management unit MMU , substantial amounts of efficient cache memory, an enhanced debug capability, digital signal processing DSP extensions, and a low-cost system interface. The resulting device is well suited to the needs of mid-range communications equipment, xDSL equipment, and consumer devices.

Also, being upwardly software compatible with the RC3000 family, the RC32364 will serve in many of the same applications as well as support applications that require integer DSP functions.

Device Performance

RC32364 is rated at 175 dhrystone MIPS at 133MHz. The internal cache bandwidth is over GB/sec, with external bus bandwidth of 260MB/sec. Computational performance is further enhanced by the device’s DSP capability, which supports 66 Million multiply-accummulate MAC operations per second at 133MHz.

The RISCore32300 uses a 5-stage pipeline, similar to the RISCore3000 and the RISCore4000 processor families. The simplicity of the pipeline enables the processor to achieve high frequency while minimizing device complexity, reducing both cost and power consumption. Because this pipeline is not sensitive to the data conflicts that slowdown super-scalar machines, an added benefit to this pipeline approach is that sustained actual performance is much closer to the theoretical maximum performance.

The RISCore32300 integer execution unit implements the MIPS 32 ISA. The RISCore32300 thus implements a load/store architecture with single-cycle ALU operations logical, shift, add, subtract and an autonomous multiply/divide unit. The 32-bit register resources include 32 general-purpose orthogonal integer registers, the HI/LO result register for the integer multiply/divide unit, and the program counter. RISCore32300 CPU core features include:
x MIPS IV prefetch operations, with various innovative hint subfields
High-order multiplexed address and data bits. Regardless of system byte ordering, AD 31 is the MSB of the address.

AD 3:0

Size 3:0 /Data 3:0

Valid sizes for the RC32364 are as follows:

Addr 3:2

ADS*

Size 3 Size 2 Size 1

Size 0
0 1 0 1 0

Transfer Width
16 bytes 1 byte 2 bytes 3 bytes 4 bytes

Other encodings allow future generations to service other transfer sizes. During the data phase, AD[3:0] represents the Data 3:0 .
Addr 3:2 Non-multiplexed address lines. These serve as the word within block address for cache refills Addr 3:2 . The word within block address bits count in a sub-block ordering.

Address Latch Enable. This signal provides set-up and hold times around the address phase of the AD bus.

Address Strobe This active-low signal indicates valid address and the start of a new bus transaction. The processor asserts ADS* for the entire address cycle. This is the inverse of the ALE signal.

Table 3 System Interface Pin Descriptions Page 1 of 4
6 of 21
*Notice The information in this document is subject to change without notice

June 20, 2000
79RC32364

Pin Width 1:0

Type

Bus Width

Indicates the Physical Memory/IO data bus size as follows:

Width 1

Width 0
0 1 0 1

Port Width
8 bits 16 bits 32 bits Reserved

BE* 3:0

ByteEnables 3:0 /Addr 1:0 Indicates which byte lanes are expected to participate in the transfer.

Port Width 32-bit 16-bit
8-bit

Byte Lanes Enabled In Data Transfer

Used

Used

Used

Used

Byte High Enable

Not Used

Address Bit 1 Byte Low

Enable

Not Used

Not Used

Address Bit 1 Address Bit 0

Driven High Driven High A1

CIP*

I/D*

DataEn*

DT/R*

Ack*

Last*

Handshake Interface
Ordering Information

IDT79RCXX YY

Product Type

Operating Voltage

XXXX

Device Type
999 Speed

A Package

A Temp range/

Process

Blank Commercial Temperature Range 0°C to +85°C Case

Industrial Temperature Range
-40°C to +85°C Case

DA 144-pin TQFP
100 MHz PClk 133 MHz PClk
364 Embedded Processor
3.3V +/-5%
79RC32 32-bit Embedded Microprocessor

Valid Combinations

IDT79RC32V364 - 100,133 DA IDT79RC32V364 - 100,133 DAI

TQFP package, Commercial Temperature TQFP package, Industrial Temperature

CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES 800-345-7015 or 408-284-8200 fax 408-284-2775

The IDT logo is a trademark of Integrated Device Technology, Inc.
21 of 21
*Notice The information in this document is subject to change without notice
for Tech Support email phone 408-284-8208

June 20, 2000

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived IDT79RC32V364-133DAG Datasheet file may be downloaded here without warranties.

Datasheet ID: IDT79RC32V364-133DAG 636642