WJLXT972MLC.A4-864115

WJLXT972MLC.A4-864115 Datasheet

Part	Datasheet
WJLXT972MLC.A4-864115	WJLXT972MLC.A4-864115 (pdf)

Related Parts	Information
WJLXT972MLC.A4-864101	WJLXT972MLC.A4-864101

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Cortina LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet The Cortina LXT972M Single-Port 10/100 Mbps PHY Transceiver LXT972M PHY directly supports both 100BASE-TX and 10BASE-T applications. The LXT972M PHY is IEEE compliant and provides a Media Independent Interface MII for easy attachment to 10/100 Media Access Controllers MACs . The LXT972M PHY supports full-duplex operation at 10 Mbps and 100 Mbps. Operating conditions for the LXT972M PHY can be set using auto-negotiation, parallel detection, or manual control. The LXT972M PHY is fabricated with an advanced CMOS process and requires only a single V power supply. - Combination 10BASE-T/100BASE-TX Network Interface Cards NICs - Wireless access points - Network printers - 10/100 Mbps PCMCIA cards - Cable Modems and Set-Top Boxes Product Features - V Operation - Carrier Sense Multiple Access / Collision - Low power consumption 300 mW typical Detection CSMA/CD or full-duplex operation - 10BASE-T and 100BASE-TX using a single RJ- - JTAG boundary scan 45 connection - MDIO serial port or hardware pin configurable - IEEE 802.3-compliant 10BASE-T or 100BASE- - Integrated, programmable LED drivers TX ports with integrated filters - 48-pin Low-profile Quad Flat Package - Auto-negotiation and parallel detection - MII interface with extended register capability - Robust baseline wander correction Legal Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH CORTINA PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN CORTINA’S TERMS AND CONDITIONS OF SALE OF SUCH PRODUCTS, CORTINA ASSUMES NO LIABILITY WHATSOEVER, AND CORTINA DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF CORTINA PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Cortina products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Cortina and the Cortina Systems logo are the trademarks or registered trademarks of Cortina Systems, Inc. and its subsidiaries in the U.S. and other countries. Other names and brands may be claimed as the property of others. Copyright 2001−2007 Cortina Systems, Inc. All rights reserved. Cortina LXT972M Single-Port 10/100 Mbps PHY Transceiver Contents Contents Introduction to This Document Document Overview 10 Related Documents Block Diagram Ball and Pin Assignments Signal Descriptions Functional Device Overview Comprehensive Functionality Optimal Signal Processing Network Media / Protocol Support 10/100 Network MII Data Interface Configuration Management Interface Operating Power Requirements Clock Requirements Initialization MDIO Control Mode and Hardware Control Reduced-Power Modes Reset Hardware Configuration Settings Establishing Link Auto-Negotiation Parallel MII Operation MII Clocks Transmit Receive Data Valid Carrier Error Signals Collision 33 Loopback Added Section Package Specifications back into Datasheet. First release of this document from Cortina Systems, Inc. Internal release. No changes. Figure 3, LXT972M Transceiver Block Diagram - Deleted ECL Driver from figure. Section Device Overview - Text changed. Section Twisted-Pair Interface - Added text on MDI crossover. Section Remote Fault Detection and Reporting - Text changed. Section External Crystal/Oscillator - Text changed. Table 37, Hardware Configuration Settings for Cortina LXT977 Transceiver - Bit value for changed. Section Parallel Detection - Text changed. Section Transmit Enable - Text changed. Section Carrier Sense - Text changed. Section Preamble Handling - Text changed. Section Link - Added text. Section Link Failure Override - Added text. Section Receive Data Valid - Text changed. Section Polarity Correction - Text changed. Section LED Pulse Stretching - Text changed. Table 123, Auto-Negotiation Next Page Transmit Register - Address 7, Hex 7 - Bits and changed. Table 124, Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8 - Bits and changed. Table 131, LED Configuration Register - Address 20, Hex 14 - Bit changed. Cortina LXT972M Single-Port 10/100 Mbps PHY Transceiver Page 8 Section Twisted-Pair Interface - Added text on MDI crossover. Section Comment for LXT972A/972M/977-->Remote Fault Detection and Reporting - Text changed. Section External Crystal/Oscillator - Text changed. Table 37, Hardware Configuration Settings for Cortina LXT977 Transceiver - Bit value for changed. Section Parallel Detection - Text changed. Section Transmit Enable - Text changed. Section Carrier Sense - Text changed. Section Preamble Handling - Text changed. Section Link - Added text. Section Link Failure Override - Added text. Section Receive Data Valid - Text changed. Section Polarity Correction - Text changed. Section LED Pulse Stretching - Text changed. Table 123, Auto-Negotiation Next Page Transmit Register - Address 7, Hex 7 - Bits and changed. Table 124, Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8 - Bits and changed. Table 131, LED Configuration Register - Address 20, Hex 14 - Bit changed. Initial release of this document. Cortina LXT972M Single-Port 10/100 Mbps PHY Transceiver Page 9 Introduction to This Document Introduction to This Document This document includes information on the Cortina LXT972M Single-Port 10/ 100 Mbps PHY Transceiver LXT972M PHY . Document Overview This document includes the following subjects Block Diagram, on page 11 Ball and Pin Assignments, on page 12 Signal Descriptions, on page 16 Functional Description, on page 21 Application Information, on page 47 Electrical Specifications, on page 51 Register Definitions - IEEE Base Registers, on page 64 Register Definitions - Product-Specific Registers, on page 72 Related Documents Table 1 Related Documents Document Title Cortina LXT971A, LXT972A, LXT972M Single-Port 10/ 100 Mbps PHY Specification Update Cortina LXT971A, LXT972A, and LXT972M V PHY Design and Layout Guide - Application Note Magnetic Manufacturers for Networking Product Applications Application Note Document Number 249354 249016 248991 Cortina LXT972M Single-Port 10/100 Mbps PHY Transceiver Page 10 Block Diagram Block Diagram Figure 1 Block Diagram RESET_L ADDR[1:0] MDIO MDC TX_EN TXD[3:0] TX_CLK LED/CFG[3:1] RX_CLK RXD[3:0] RX_DV CRS RX_ER Management / Mode Select Logic Register Set Clock Generator Power Supply For additional product and ordering information To provide comments on this document: Cortina LXT972M Single-Port 10/100 Mbps PHY Transceiver ~ End of Document ~ Page 81

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Cortina LXT972M Single-Port 10/100 Mbps PHY Transceiver

Datasheet

The Cortina LXT972M Single-Port 10/100 Mbps PHY Transceiver LXT972M PHY directly supports both 100BASE-TX and 10BASE-T applications. The LXT972M PHY is IEEE compliant and provides a Media Independent Interface MII for easy attachment to 10/100 Media Access Controllers MACs . The LXT972M PHY supports full-duplex operation at 10 Mbps and 100 Mbps. Operating conditions for the LXT972M PHY can be set using auto-negotiation, parallel detection, or manual control. The LXT972M PHY is fabricated with an advanced CMOS process and requires only a single V power supply.
- Combination 10BASE-T/100BASE-TX Network Interface Cards NICs
- Wireless access points - Network printers
- 10/100 Mbps PCMCIA cards - Cable Modems and Set-Top Boxes

Product Features
- V Operation
- Carrier Sense Multiple Access / Collision
- Low power consumption 300 mW typical

Detection CSMA/CD or full-duplex operation
- 10BASE-T and 100BASE-TX using a single RJ- - JTAG boundary scan
45 connection
- MDIO serial port or hardware pin configurable
- IEEE 802.3-compliant 10BASE-T or 100BASE- - Integrated, programmable LED drivers

TX ports with integrated filters
- 48-pin Low-profile Quad Flat Package
- Auto-negotiation and parallel detection
- MII interface with extended register capability
- Robust baseline wander correction

Legal Disclaimers

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH CORTINA PRODUCTS.

NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.

EXCEPT AS PROVIDED IN CORTINA’S TERMS AND CONDITIONS OF SALE OF SUCH PRODUCTS, CORTINA ASSUMES NO LIABILITY WHATSOEVER, AND CORTINA DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF CORTINA PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Cortina products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Cortina and the Cortina Systems logo are the trademarks or registered trademarks of Cortina Systems, Inc. and its subsidiaries in the U.S. and other countries. Other names and brands may be claimed as the property of others.

Copyright 2001−2007 Cortina Systems, Inc. All rights reserved.

Cortina LXT972M Single-Port 10/100 Mbps PHY Transceiver

Contents

Contents

Introduction to This Document

Document Overview 10 Related Documents

Block Diagram

Ball and Pin Assignments

Signal Descriptions

Functional

Device Overview Comprehensive Functionality Optimal Signal Processing

Network Media / Protocol Support 10/100 Network MII Data Interface Configuration Management Interface

Operating Power Requirements Clock Requirements

Initialization MDIO Control Mode and Hardware Control Reduced-Power Modes Reset Hardware Configuration Settings

Establishing Link Auto-Negotiation Parallel

MII Operation MII Clocks Transmit Receive Data Valid Carrier Error Signals Collision 33 Loopback
Added Section Package Specifications back into Datasheet.

First release of this document from Cortina Systems, Inc.

Internal release. No changes.

Figure 3, LXT972M Transceiver Block Diagram - Deleted ECL Driver from figure. Section Device Overview - Text changed. Section Twisted-Pair Interface - Added text on MDI crossover. Section Remote Fault Detection and Reporting - Text changed. Section External Crystal/Oscillator - Text changed. Table 37, Hardware Configuration Settings for Cortina LXT977 Transceiver - Bit value for changed. Section Parallel Detection - Text changed. Section Transmit Enable - Text changed. Section Carrier Sense - Text changed. Section Preamble Handling - Text changed. Section Link - Added text. Section Link Failure Override - Added text. Section Receive Data Valid - Text changed. Section Polarity Correction - Text changed. Section LED Pulse Stretching - Text changed. Table 123, Auto-Negotiation Next Page Transmit Register - Address 7, Hex 7 - Bits and changed. Table 124, Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8 - Bits and changed. Table 131, LED Configuration Register - Address 20, Hex 14 - Bit changed.

Cortina LXT972M Single-Port 10/100 Mbps PHY Transceiver

Page 8

Section Twisted-Pair Interface - Added text on MDI crossover. Section Comment for LXT972A/972M/977-->Remote Fault Detection and Reporting - Text changed. Section External Crystal/Oscillator - Text changed. Table 37, Hardware Configuration Settings for Cortina LXT977 Transceiver - Bit value for changed. Section Parallel Detection - Text changed. Section Transmit Enable - Text changed. Section Carrier Sense - Text changed. Section Preamble Handling - Text changed. Section Link - Added text. Section Link Failure Override - Added text. Section Receive Data Valid - Text changed. Section Polarity Correction - Text changed. Section LED Pulse Stretching - Text changed. Table 123, Auto-Negotiation Next Page Transmit Register - Address 7, Hex 7 - Bits and changed. Table 124, Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8 - Bits and changed. Table 131, LED Configuration Register - Address 20, Hex 14 - Bit changed.

Initial release of this document.

Cortina LXT972M Single-Port 10/100 Mbps PHY Transceiver

Page 9

Introduction to This Document

Introduction to This Document

This document includes information on the Cortina LXT972M Single-Port 10/ 100 Mbps PHY Transceiver LXT972M PHY .

Document Overview

This document includes the following subjects Block Diagram, on page 11 Ball and Pin Assignments, on page 12 Signal Descriptions, on page 16 Functional Description, on page 21 Application Information, on page 47 Electrical Specifications, on page 51 Register Definitions - IEEE Base Registers, on page 64 Register Definitions - Product-Specific Registers, on page 72

Related Documents

Table 1

Related Documents

Document Title

Cortina LXT971A, LXT972A, LXT972M Single-Port 10/ 100 Mbps PHY Specification Update Cortina LXT971A, LXT972A, and LXT972M V PHY Design and Layout Guide - Application Note Magnetic Manufacturers for Networking Product Applications Application Note

Document Number 249354
249016
248991

Cortina LXT972M Single-Port 10/100 Mbps PHY Transceiver

Page 10

Block Diagram

Block Diagram

Figure 1 Block Diagram

RESET_L ADDR[1:0]

MDIO MDC

TX_EN TXD[3:0]

TX_CLK

LED/CFG[3:1]

RX_CLK RXD[3:0]

RX_DV CRS

RX_ER

Management /

Mode Select Logic

Register Set

Clock Generator

Power Supply
For additional product and ordering information To provide comments on this document:

Cortina LXT972M Single-Port 10/100 Mbps PHY Transceiver
~ End of Document ~

Page 81

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Datasheet ID: WJLXT972MLC.A4-864115 506895