SAB82532H10V32A

SAB82532H10V32A Datasheet

Enhanced Serial Communication Controller ESCC2 SAB 82532 SAF 82532 Version

Part	Datasheet
SAB82532H10V32A	SAB82532H10V32A (pdf)

Related Parts	Information
SAF82532N10V32A	SAF82532N10V32A

PDF Datasheet Preview
ICs for Communications Enhanced Serial Communication Controller ESCC2 SAB 82532 SAF 82532 Version User’s Manual Current Version: Previous Version User’s Manual Page in previous Version Page in new Version new package provided P-MQFP-80 Selectable out-of-band flow control in ASYNC mode description added In-band flow control transparency description added Selectable enhanced resolution BRG description added 110, 141, 167 124, 170, 208 Timer register TIMR description extended for V3.x 107, 127 120, 149 RSTA register, ISR0 register RME interrupt description extended 115, 146, 172 133, 179, 217 XBCH, bit XC description extended 124,152, 179 144, 187, 227 Baud rate generator register BGR description extended Channel configuration register 4 CCR4 in HDLC mode description extended STAR, bit XFW description extended Mode register MODE in ASYNC mode new bits FRTS, FRCS RFIFO Control Register RFC in ASYNC mode new bit DXS 198, 237 Channel Configuration Register 4 CCR4 in ASYNC and BISYNC mode new register XTAL1 clock period, high time and low time min. values for N-10 version corrected Edition This edition was realized using the software system Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München Siemens AG All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide see address list . Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. Ordering Code Q67101-H6790 Q67101-H6791 Q67101-H6788 Q67101-H6789 on request on request Package P-LCC-68 P-LCC-68 P-MQFP-80 P-MQFP-80 P-LCC-68 P-MQFP-80 Max. Data Rate Time Slot Mode ext. int. DPLL clocked Mbit/s 2 Mbit/s no 10 Mbit/s 2 Mbit/s yes Mbit/s 2 Mbit/s no 10 Mbit/s 2 Mbit/s yes 10 Mbit/s 2 Mbit/s yes 10 Mbit/s 2 Mbit/s yes Semiconductor Group SAB 82532/SAF 82532 Introduction • Support of bus configuration by collision detection and resolution • Statistical multiplexing • Continuous transmission of 1 to 32 bytes possible • Programmable preamble 8 bit with selectable repetition rate HDLC/SDLC and BISYNC • Data rate up to 10 Mbit/s • Master clock mode with data rate up to 4 Mbit/s Protocol Support HDLC/SDLC • Various types of protocol support depending on operating mode Auto mode automatic handling of S- and I-frames Non-auto mode Transparent mode • Handling of bit oriented functions • Support of LAPB/LAPD/SDLC/HDLC protocol in auto mode I- and S-frame handling • Modulo-8 or modulo-128 operation • Programmable time-out and retry conditions • Programmable maximum packet size checking MP Interface and Ports • 64 byte FIFOs per channel and direction byte or word access • 8/16 bit microprocessor bus interface Intel or Motorola type • All registers directly accessible byte and word access • Efficient transfer of data blocks from/to system memory via DMA or interrupt request • Support of Daisy Chaining and Slave Operation with Interrupt Vector generation • 8-bit programmable bi-directional universal port General • Advanced CMOS technology • Low power consumption active 40 mW at 2 MHz/standby 5 mW typical values • P-LCC-68 Package • P-MQFP-80 Package Semiconductor Group Pin Configuration top view SAB 82532/SAF 82532 Introduction P-LCC-68 Figure 1 Semiconductor Group SAB 82532/SAF 82532 Ordering Code Q67100-H6222 Semiconductor Group SAB 82532/SAF 82532 Figure 71 Block Diagram EASY532 Semiconductor Group SAB 82532/SAF 82532 Semiconductor Group

PDF Datasheet Preview

ICs for Communications

Enhanced Serial Communication Controller ESCC2 SAB 82532 SAF 82532 Version

User’s Manual

Current Version:

Previous Version User’s Manual

Page in previous Version

Page in new Version
new package provided P-MQFP-80

Selectable out-of-band flow control in ASYNC mode description added

In-band flow control transparency description added

Selectable enhanced resolution BRG description added
110, 141, 167 124, 170, 208 Timer register TIMR description extended for V3.x
107, 127
120, 149

RSTA register, ISR0 register RME interrupt description extended
115, 146, 172 133, 179, 217 XBCH, bit XC description extended
124,152, 179 144, 187, 227 Baud rate generator register BGR description extended

Channel configuration register 4 CCR4 in HDLC mode description extended

STAR, bit XFW description extended

Mode register MODE in ASYNC mode new bits FRTS, FRCS

RFIFO Control Register RFC in ASYNC mode new bit DXS
198, 237

Channel Configuration Register 4 CCR4 in ASYNC and BISYNC mode new
register

XTAL1 clock period, high time and low time min. values for N-10 version
corrected

Edition This edition was realized using the software system

Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München

Siemens AG

All Rights Reserved.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics.

Terms of delivery and rights to change design reserved.

For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide see address list .

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group.

Siemens AG is an approved CECC manufacturer.

Packing

Please use the recycling operators known to you. We can also help you get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.

Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG.
Ordering Code

Q67101-H6790 Q67101-H6791 Q67101-H6788 Q67101-H6789 on request on request

Package

P-LCC-68 P-LCC-68 P-MQFP-80 P-MQFP-80 P-LCC-68 P-MQFP-80

Max. Data Rate

Time Slot

Mode
ext.
int. DPLL
clocked

Mbit/s 2 Mbit/s no
10 Mbit/s
2 Mbit/s yes

Mbit/s 2 Mbit/s no
10 Mbit/s
2 Mbit/s yes
10 Mbit/s
2 Mbit/s yes
10 Mbit/s
2 Mbit/s yes

Semiconductor Group

SAB 82532/SAF 82532

Introduction
• Support of bus configuration by collision detection and resolution
• Statistical multiplexing
• Continuous transmission of 1 to 32 bytes possible
• Programmable preamble 8 bit with selectable
repetition rate HDLC/SDLC and BISYNC
• Data rate up to 10 Mbit/s
• Master clock mode with data rate up to 4 Mbit/s

Protocol Support HDLC/SDLC
• Various types of protocol support depending on operating mode Auto mode automatic handling of S- and I-frames Non-auto mode Transparent mode
• Handling of bit oriented functions
• Support of LAPB/LAPD/SDLC/HDLC protocol in auto mode

I- and S-frame handling
• Modulo-8 or modulo-128 operation
• Programmable time-out and retry conditions
• Programmable maximum packet size checking

MP Interface and Ports
• 64 byte FIFOs per channel and direction byte or word access
• 8/16 bit microprocessor bus interface Intel or Motorola type
• All registers directly accessible byte and word access
• Efficient transfer of data blocks from/to system memory via DMA or interrupt request
• Support of Daisy Chaining and Slave Operation with Interrupt Vector generation
• 8-bit programmable bi-directional universal port

General
• Advanced CMOS technology
• Low power consumption active 40 mW at 2 MHz/standby 5 mW typical values
• P-LCC-68 Package
• P-MQFP-80 Package

Semiconductor Group

Pin Configuration top view

SAB 82532/SAF 82532

Introduction

P-LCC-68

Figure 1

Semiconductor Group

SAB 82532/SAF 82532
Ordering Code Q67100-H6222

Semiconductor Group

SAB 82532/SAF 82532

Figure 71 Block Diagram EASY532

Semiconductor Group

SAB 82532/SAF 82532

Semiconductor Group

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived SAB82532H10V32A Datasheet file may be downloaded here without warranties.

Datasheet ID: SAB82532H10V32A 638528