PXB 4221 E V3.4-G
PXB 4221 E V3.4-G Datasheet
Interworking Element for 8 E1/T1 Lines PXB 4219E, PXB 4220E, PXB 4221E, Version
| Part | Datasheet |
|---|---|
PXB 4221 E V3.4-G |
PXB 4221 E V3.4-G (pdf) |
| Related Parts | Information |
|---|---|
PXB4220E-V32 |
PXB4220E-V32 |
PXB4220E-V33 |
PXB4220E-V33 |
PXB 4220 E V3.4-G |
PXB 4220 E V3.4-G |
PXB 4219 E V3.4 |
PXB 4219 E V3.4 |
| PDF Datasheet Preview |
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| Data Sheet, DS3, Jan. 2003 IWE8 Interworking Element for 8 E1/T1 Lines PXB 4219E, PXB 4220E, PXB 4221E, Version Wired Communications Never stop thinking. Data Sheet 2003-01-20 Previous Version: Preliminary Data Sheet, DS2, 2002-05-06 are registered trademarks of Infineon Technologies AG. 10BaseS , EasyPort , VDSLite are trademarks of Infineon Technologies AG. is a registered trademark of Microsoft Corporation. is a registered trademark of Linus Torvalds. The information in this document is subject to change without notice. Edition 2003-01-20 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. IWE8, V3.4 PXB 4219E, PXB 4220E, PXB 4221E Table of Contents Overview 14 Features 15 Logic Symbol 17 Typical Applications 18 Line Card 19 Echo Canceller 19 Differences Between PXB4220 And PXB4219 21 Differences Between PXB4220 And PXB4221 21 Pin Descriptions 22 Pin Diagram 22 Pin Definitions and Functions 23 Generic Framer Interface 23 UTOPIA Interface 25 IMA Interface 27 Clock Recovery Interface 28 Microprocessor Interface 28 External RAM Interface 30 Test Interface 31 Miscellaneous 32 Power Supply 33 Not Connected Pins 33 Functional Description 34 Operating Modes 35 ATM Mode 35 AAL Mode 35 Unstructured CES Mode 35 Structured CES Mode 36 Functional Block Diagram 37 Functional Block Description 38 Operational Description 42 ATM Transmit Functions 42 Operation 42 ATM Transmit Buffer Filling Level 42 Cell Discarding 43 Cell rate de-coupling Idle/Unassigned Cell Insertion 43 Cell Payload Scrambling 44 HEC Generation 44 Setup of ATM Transmit Ports 45 ATM Receive Functions 46 Operation 46 Cell Delineation 46 Data Sheet 2003-01-20 IWE8, V3.4 PXB 4219E, PXB 4220E, PXB 4221E Table of Contents HEC Check Header Error Detection and Correction 48 Cell Payload Descrambling 49 Idle, Physical Layer or Unassigned Cell Deletion 49 Data on the system internal highway is structured in frames of 256 bits every 125 µs. It is transmitted in 32 slots numbered from 0 to 31 with slot 0 transmitted first. The data bits of a slot are numbered from 1 to The first transmitted bit ‘bit 1’ is the most significant bit. Figure 23 shows the bit ordering. Data Sheet 2003-01-20 IWE8, V3.4 PXB 4219E, PXB 4220E, PXB 4221E Interface Description Framer Receive Interface FRCLKn FRDATn FRMFBn B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 248 249 250 251 252 253 254 255 256 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FRFRSn timeslot 31 Framer Transmit Interface FTCKOn timeslot 0 timeslot 1 FTDATn FTMFSn B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 248 249 250 251 252 253 254 255 256 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FTFRSn timeslot 31 Figure 23 Framer Interface in FAM timeslot 0 timeslot 1 Fifam T1 FALC Mode In T1 mode Pin E1/T1 = 0 there is one F-channel carrying the F-bit Frame Alignment Signal/Data Link FS/DL and 24 data channels numbered from 1 to When using the QuadFALC in translation mode 0 See QuadFALC data sheet these channels are mapped into the 32 frame slots as shown in Table 25 Table 25 Time slot Mapping in T1 Translation Mode 0 Frame slot T1 channel Frame slot T1 channel F channel FS/DL channel 1 channel 13 channel 2 channel 14 channel 3 channel 15 channel 4 channel 16 channel 5 channel 17 channel 6 |
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