PEF 20550 H V2.1

PEF 20550 H V2.1 Datasheet

Extended Line Card Interface Controller PEB 20550 PEF 20550 Versions

Part	Datasheet
PEF 20550 H V2.1	PEF 20550 H V2.1 (pdf)

PDF Datasheet Preview
ICs for Communications Extended Line Card Interface Controller PEB 20550 PEF 20550 Versions User’s Manual T2055-0V13-M1-7600 Edition This edition was realized using the software system Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München Siemens AG All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide see address list . Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended a to be implanted in the human body, or b to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. Previous Release: Page in Previous Release Page in User’s Manual PEF 20550 ext. temperature range new System Integration and Application DECT added Boundary scan number 22 = 110 correction Boundary scan number 9 ID code for V1.3 added Boundary scan ID code for V1.3 added DMA-transfers, figure 31 new Support of the HDLC protocol by SACCO, figure 35 new SACCO clock mode 2 description extended Extensions for V1.3 Arbiter state machine description extended Table 14 Control channel delay examples extended Internal reference clock RCL replaced by CFI reference clock CRCL Interrupt driven transmission sequence example, figure 50 new Internal reference clock RCL replaced by CFI reference clock CRCL Register address arrangement extended EMOD ECMD2 restriction 5 new PMOD PMD1..0 description data rate stepping corrected CMD2 CXF, CRR description corrected MACR description extended TIMR SSR correction VNSR VN3..0 = V1.2 correction EXIR XMR description extended CCR1 ODS description extended for V1.3 SACCO RSTA C/R description new VSTR VN3..0 value for V1.3 added SCV SCV7...0 description extended Application Hints new tALS min = 8 ns, tDRH max = 65 ns, tAH min = 0 ns correction Package outlines new Appendix new PEB 20550 Table of Contents Overview Features Pin Configuration top view Pin Definitions and Functions Logic Symbol Functional Block Diagram System Integration and Application Digital Line Card Switching, Layer-1 Control, Group Controller Signaling Decentralized D-Channel Processing, Multiplexed HDLC-Controller. Decentralized D-Channel Processing, Dedicated HDLC-Controller per Subscriber Decentralized D-Channel Processing, Multiplexed plus Dedicated HDLC-Control Central D-Channel Processing Mixed D-Channel Processing, Signaling Decentralized, Packet Data Centralized Key Systems Analog Line Card DECT Applications Adaptation of a DECT System to an Existing PBX DECT Line Card Design for an Existing PBX Functional Description. General Functions and Device Architecture Functional Blocks Bus Interface Parallel Ports Watchdog Timer Reset Logic Boundary Scan Support Boundary Scan TAP-Controller PCM-Interface Configurable Interface Memory Structure and Switching Pre-processed Channels, Layer-1 Support Special Functions SACCO Block Diagram Parallel Interface FIFO-Structure Semiconductor Group PEB 20550 Table of Contents Protocol Support Special Functions Serial Interface Serial Port Configuration Test Mode D-Channel Arbiter Upstream Direction Downstream Direction Control Channel Delay D-Channel Arbiter Co-operating with QUAT-S Circuits Operational Description Microprocessor Interface Operation Interrupt Structure and Logic Clocking Reset Operation PCM-Interface Configurable Interface Switching Functions Special Functions SACCO-A/B Data Transmission in Interrupt Mode Data Transmission in DMA-Mode Data Reception in Interrupt Mode Data Reception in DMA-Mode D-Channel Arbiter SACCO-A Transmission SACCO-A Reception Initialization Procedure Hardware Reset Initialization Register Initialization Control Memory Reset Initialization of Pre-processed Channels Initialization of the Upstream Data Memory DM Tristate Field SACCO-Initialization of D-Channel Arbiter Activation of the PCM- and CFI-Interfaces Initialization Example Initialization Example SACCO-A Initialization Example D-Channel Arbiter Initialization Example Semiconductor Group PEB 20550 Table of Contents PCM- and CFI-Interface Activation Example SACCO-B Initialization Example Ordering Code Q67101-H6484 Q67101-H6605 Package P-MQFP-80-1 SMD P-MQFP-80-1 SMD PEB 20550 PEF 20550 Overview Handling of Layer-1 Functions • Change detection for C/I-channel IOM-configuration or feature control SLD-configuration • Additional last-look logic for feature control SLD-configuration • Buffered monitor IOM-configuration or signaling channel SLD-configuration Handling of Layer-2 Functions SACCO • Two independent full duplex HDLC-channels Serial interface Data rate up to 4 Mbit/s Independent time slot assignment for each channel with programmable time slot length 1-256 bits Support of bus configuration with collision resolution Continuous transmission of 1 to 32 bytes possible Protocol support Auto-mode, fully compatible to PEB 2050 PBC protocol Non-auto mode, address recognition capability Transparent mode, HDLC-framing only Extended transparent mode, fully transparent without HDLC-framing 64-bytes FIFO’s per HDLC-channel and direction D-channel Multiplexing D-channel arbiter • Serving of multiple subscribers with one HDLC-controller • Full duplex signaling protocols e.g. LAPD or proprietary supported • Programmable priority scheme • Broadcast transmission Line Card Glue Logic • Power-up reset generator • Watchdog timer • Parallel ports 8-bit input, 4-bit I/O Boundary Scan Support • Fully IEEE compatible • 32-bit device identification register Bus Interface • Siemens/Intel or Motorola type µP-interface • 8-bit demultiplexed bus interface • FIFO-access interrupt or DMA controlled Semiconductor Group Pin Configuration top view PEB 20550 PEF 20550 Overview RxD1 RxD2 RxD3 VSS RxDB CxDB TxDB TSCB HDCB VDD HFSB HFSA HDCA TSCA TxDA CxDA RxDA DRQTA DRQRA DRQTB RxD0 TSC0 TxD0 TSC1 TxD1 TSC2 TxD2 TSC3 TxD3 PFS PDC VSS TCK TDO TDI TMS P0.0, A0 P0.1, A1 P0.2, A2 P0.3, A3 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PEB 20550 ELIC R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DRQRB DACKA DACKB DD3/SIP3 DD2/SIP2 DD1/SIP1 DD0/SIP0 DU3/SIP7 DU2/SIP6 VSS DU1/SIP5 DU0/SIP4 DCL FSC RESEX RESIN P1.3 P1.2 P1.1 P1.0 P0.4, A4 P0.5, A5 P0.6, A6 P0.7, A7 INT CSE CSS WR, R/W RD, DS ALE VDD AD0, D0 AD1, D1 AD2, D2 AD3, D3 AD4, D4 AD5, D5 AD6, D6 AD7, D7 VSS ITP05803 Figure 2 Semiconductor Group Pin Definitions and Functions PEB 20550 PEF 20550 Overview µ-Processor Interface Pin No. Symbol Input I Function Output O Chip Select EPIC-1 active low. A "low" on this line selects all registers excluding the SACCOregisters for read/write operations. Chip Select SACCO active low. A "low" on this line selects the SACCO-registers for read/write operations. Write, active low, Siemens/Intel bus mode. When "low", a write operation is indicated. Read/Write, Motorola bus mode. When "high" a valid µP-access identifies a read operation, when "low" it identifies a write access. RD, DS I Read, active low, Siemens/Intel bus mode. When "low" a read operation is indicated. Data Strobe, Motorola bus mode. A rising edge marks the end of a read or write operation. Ordering Code Q67100-H8647 SAC 3 SAC 2 SAC 1 AMC 3 80C188 CPU System AMC 2 Dual Port RAM AMC 1 PC Interface ITB05758 Figure 150 The SIPB 5000 Mainboard is the general backbone of the SIPB 5XXX user board system. It is designed as a standard PC interface card, and it contains basically a 80C188 CPU system with 7 interfaces. The interface to the PC is realized both as a Dual Port Ram and as an additional DMA interface. Up to three daughter modules see dotted blocks can be added to the Mainboard. They typically carry the components under evaluation. The interfaces which are accessible from the back side of the PC have a connection to the daughter modules as well. This is to allow access to the components under evaluation while the complete board system is hidden inside the PC. Semiconductor Group SIPB 5122 Line Card Module PEB 20550 PEF 20550 IOM-2 Line Card Module ELIC Part Number SIPB 5122 Ordering Code Q67100-H6397 SLD/IOM R /PCM ELIC R PEB 20550 SAC AMC HSCX SAB 82525 ITB05760 Figure 151 The Line Card Module SIBP 5122 is designed to be used with the ISDN User Board SIPB It serves as an evaluation tool for various line card architectures using the Extended Line Card Interface Controller ELIC PEB Possible applications are e.g.: Centralized / decentralized D-channel handling of signaling and packet data Emulation of a PABX with primary rate module SIPB 7200 Emulation of a small PABX using two line cards Emulation of a digital or analog line card using appropriate layer-1 and/ or CODEC filter modules Semiconductor Group Lists Glossary Audio ringing codec filter Bits per PCM frame Configurable interface Control memory Central office Data clock Extended line interface controller Extended PCM interface controller ETSI European telecommunication standards institute FIFO First-in first-out memory Frame synchronisation clock HDCB HDLC data clock channel B HDLC High-level data link control Integrated circuit Identifier ISDN oriented modular ISDN subscriber access controller on U-interface Octal transceiver for UPN-interfaces Peripheral bus controller Private branch exchange Pulse code modulation PCM interface data clock

PDF Datasheet Preview

ICs for Communications

Extended Line Card Interface Controller PEB 20550 PEF 20550 Versions

User’s Manual

T2055-0V13-M1-7600

Edition

This edition was realized using the software system

Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München

Siemens AG

All Rights Reserved.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics.

Terms of delivery and rights to change design reserved.

For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide see address list .

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group.

Siemens AG is an approved CECC manufacturer.

Packing

Please use the recycling operators known to you. We can also help you get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.

Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
2 Life support devices or systems are intended a to be implanted in the human body, or b to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.

Previous Release:

Page in Previous Release

Page in User’s Manual

PEF 20550 ext. temperature range new System Integration and Application DECT added Boundary scan number 22 = 110 correction Boundary scan number 9 ID code for V1.3 added Boundary scan ID code for V1.3 added DMA-transfers, figure 31 new Support of the HDLC protocol by SACCO, figure 35 new SACCO clock mode 2 description extended Extensions for V1.3 Arbiter state machine description extended Table 14 Control channel delay examples extended Internal reference clock RCL replaced by CFI reference clock CRCL Interrupt driven transmission sequence example, figure 50 new Internal reference clock RCL replaced by CFI reference clock CRCL Register address arrangement extended EMOD ECMD2 restriction 5 new PMOD PMD1..0 description data rate stepping corrected CMD2 CXF, CRR description corrected MACR description extended TIMR SSR correction VNSR VN3..0 = V1.2 correction EXIR XMR description extended CCR1 ODS description extended for V1.3 SACCO RSTA C/R description new VSTR VN3..0 value for V1.3 added SCV SCV7...0 description extended Application Hints new
tALS min = 8 ns, tDRH max = 65 ns, tAH min = 0 ns correction

Package outlines new Appendix new

PEB 20550

Table of Contents

Overview Features Pin Configuration top view Pin Definitions and Functions Logic Symbol Functional Block Diagram System Integration and Application Digital Line Card Switching, Layer-1 Control, Group Controller Signaling Decentralized D-Channel Processing, Multiplexed HDLC-Controller. Decentralized D-Channel Processing, Dedicated HDLC-Controller per Subscriber Decentralized D-Channel Processing, Multiplexed plus Dedicated HDLC-Control Central D-Channel Processing Mixed D-Channel Processing, Signaling Decentralized, Packet Data Centralized Key Systems Analog Line Card DECT Applications Adaptation of a DECT System to an Existing PBX DECT Line Card Design for an Existing PBX

Functional Description. General Functions and Device Architecture Functional Blocks Bus Interface Parallel Ports Watchdog Timer Reset Logic Boundary Scan Support Boundary Scan TAP-Controller PCM-Interface Configurable Interface Memory Structure and Switching Pre-processed Channels, Layer-1 Support Special Functions SACCO Block Diagram Parallel Interface FIFO-Structure

Semiconductor Group

PEB 20550

Table of Contents

Protocol Support Special Functions Serial Interface Serial Port Configuration Test Mode D-Channel Arbiter Upstream Direction Downstream Direction Control Channel Delay D-Channel Arbiter Co-operating with QUAT-S Circuits

Operational Description Microprocessor Interface Operation Interrupt Structure and Logic Clocking Reset Operation PCM-Interface Configurable Interface Switching Functions Special Functions SACCO-A/B Data Transmission in Interrupt Mode Data Transmission in DMA-Mode Data Reception in Interrupt Mode Data Reception in DMA-Mode D-Channel Arbiter SACCO-A Transmission SACCO-A Reception Initialization Procedure Hardware Reset Initialization Register Initialization Control Memory Reset Initialization of Pre-processed Channels Initialization of the Upstream Data Memory DM Tristate Field SACCO-Initialization of D-Channel Arbiter Activation of the PCM- and CFI-Interfaces Initialization Example Initialization Example SACCO-A Initialization Example D-Channel Arbiter Initialization Example

Semiconductor Group

PEB 20550

Table of Contents

PCM- and CFI-Interface Activation Example SACCO-B Initialization Example
Ordering Code Q67101-H6484 Q67101-H6605

Package P-MQFP-80-1 SMD P-MQFP-80-1 SMD

PEB 20550 PEF 20550

Overview

Handling of Layer-1 Functions
• Change detection for C/I-channel IOM-configuration or feature control

SLD-configuration
• Additional last-look logic for feature control SLD-configuration
• Buffered monitor IOM-configuration or signaling channel SLD-configuration

Handling of Layer-2 Functions SACCO
• Two independent full duplex HDLC-channels

Serial interface Data rate up to 4 Mbit/s Independent time slot assignment for each channel with programmable time slot length 1-256 bits Support of bus configuration with collision resolution Continuous transmission of 1 to 32 bytes possible

Protocol support Auto-mode, fully compatible to PEB 2050 PBC protocol Non-auto mode, address recognition capability Transparent mode, HDLC-framing only Extended transparent mode, fully transparent without HDLC-framing
64-bytes FIFO’s per HDLC-channel and direction

D-channel Multiplexing D-channel arbiter
• Serving of multiple subscribers with one HDLC-controller
• Full duplex signaling protocols e.g. LAPD or proprietary supported
• Programmable priority scheme
• Broadcast transmission

Line Card Glue Logic
• Power-up reset generator
• Watchdog timer
• Parallel ports 8-bit input, 4-bit I/O

Boundary Scan Support
• Fully IEEE compatible
• 32-bit device identification register

Bus Interface
• Siemens/Intel or Motorola type µP-interface
• 8-bit demultiplexed bus interface
• FIFO-access interrupt or DMA controlled

Semiconductor Group

Pin Configuration top view

PEB 20550 PEF 20550

Overview

RxD1 RxD2 RxD3 VSS RxDB CxDB TxDB TSCB HDCB VDD HFSB HFSA HDCA TSCA TxDA CxDA RxDA DRQTA DRQRA DRQTB

RxD0 TSC0 TxD0 TSC1 TxD1 TSC2 TxD2 TSC3 TxD3 PFS PDC

VSS TCK TDO TDI TMS P0.0, A0 P0.1, A1 P0.2, A2 P0.3, A3
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

PEB 20550

ELIC R
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

DRQRB DACKA DACKB DD3/SIP3 DD2/SIP2 DD1/SIP1 DD0/SIP0 DU3/SIP7 DU2/SIP6 VSS DU1/SIP5 DU0/SIP4 DCL FSC RESEX RESIN P1.3 P1.2 P1.1 P1.0

P0.4, A4 P0.5, A5 P0.6, A6 P0.7, A7

INT CSE CSS WR, R/W RD, DS ALE VDD AD0, D0 AD1, D1 AD2, D2 AD3, D3 AD4, D4 AD5, D5 AD6, D6 AD7, D7 VSS

ITP05803

Figure 2

Semiconductor Group

Pin Definitions and Functions

PEB 20550 PEF 20550

Overview
µ-Processor Interface

Pin No. Symbol Input I Function Output O

Chip Select EPIC-1 active low. A "low" on this line selects all registers excluding the SACCOregisters for read/write operations.

Chip Select SACCO active low. A "low" on this line selects the SACCO-registers for read/write operations.

Write, active low, Siemens/Intel bus mode. When "low", a write operation is indicated. Read/Write, Motorola bus mode. When "high" a valid µP-access identifies a read operation, when "low" it identifies a write access.

RD, DS I

Read, active low, Siemens/Intel bus mode. When "low" a read operation is indicated. Data Strobe, Motorola bus mode. A rising edge marks the end of a read or write operation.
Ordering Code Q67100-H8647

SAC 3 SAC 2 SAC 1

AMC 3
80C188 CPU System

AMC 2

Dual Port RAM

AMC 1

PC Interface

ITB05758

Figure 150

The SIPB 5000 Mainboard is the general backbone of the SIPB 5XXX user board system. It is designed as a standard PC interface card, and it contains basically a 80C188 CPU system with 7 interfaces. The interface to the PC is realized both as a Dual Port Ram and as an additional DMA interface. Up to three daughter modules see dotted blocks can be added to the Mainboard. They typically carry the components under evaluation. The interfaces which are accessible from the back side of the PC have a connection to the daughter modules as well. This is to allow access to the components under evaluation while the complete board system is hidden inside the PC.

Semiconductor Group

SIPB 5122 Line Card Module

PEB 20550 PEF 20550

IOM-2 Line Card Module ELIC

Part Number SIPB 5122
Ordering Code Q67100-H6397

SLD/IOM R /PCM

ELIC R

PEB 20550

SAC AMC

HSCX

SAB 82525

ITB05760

Figure 151

The Line Card Module SIBP 5122 is designed to be used with the ISDN User Board SIPB It serves as an evaluation tool for various line card architectures using the Extended Line Card Interface Controller ELIC PEB

Possible applications are e.g.:

Centralized / decentralized D-channel handling of signaling and packet data Emulation of a PABX with primary rate module SIPB 7200 Emulation of a small PABX using two line cards Emulation of a digital or analog line card using appropriate layer-1 and/ or CODEC
filter modules

Semiconductor Group

Lists

Glossary

Audio ringing codec filter

Bits per PCM frame

Configurable interface

Control memory

Central office

Data clock

Extended line interface controller

Extended PCM interface controller

ETSI

European telecommunication standards institute

FIFO

First-in first-out memory

Frame synchronisation clock

HDCB HDLC data clock channel B

HDLC

High-level data link control

Integrated circuit

Identifier

ISDN oriented modular

ISDN subscriber access controller on U-interface

Octal transceiver for UPN-interfaces

Peripheral bus controller

Private branch exchange

Pulse code modulation

PCM interface data clock

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived PEF20550HV2.1 Datasheet file may be downloaded here without warranties.

Datasheet ID: PEF20550HV2.1 638465