PEF 22504 HT V2.1

PEF 22504 HT V2.1 Datasheet

Quad E1/T1/J1 Line Interface Component for Long- and Short-Haul Applications PEF 22504 E, PEF 22504 HT, Version

Part	Datasheet
PEF 22504 HT V2.1	PEF 22504 HT V2.1 (pdf)

Related Parts	Information
PEF 22504 E V2.1-G	PEF 22504 E V2.1-G

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QuadLIUTM Quad E1/T1/J1 Line Interface Component for Long- and Short-Haul Applications PEF 22504 E, PEF 22504 HT, Version Communications Edition 2006-01-25 Published by Infineon Technologies AG, 81726 München, Germany Infineon Technologies AG All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. QuadLIUTM PEF 22504 PEF 22504 E, Quad E1/T1/J1 Line Interface Component for Long- and Short-Haul Applications Previous Version Preliminary Data Sheet 2005-11-07 Chapter 5 The QuadLIUTM is now available in PG-TQFP-144-17 package also Trademarks are registered trademarks of Infineon Technologies AG. 10BaseS , EasyPort , VDSLite are trademarks of Infineon Technologies AG. is a registered trademark of Microsoft Corporation, of Linus Torvalds, of Visio Corporation, and of Adobe Systems Incorporated. Data Sheet QuadLIUTM PEF 22504 Table of Contents Preface 11 Introduction 12 Features 13 Logic Symbol 15 Typical Applications 16 Pin Descriptions 17 Ball Diagram P/PG-LBGA-160-1 top view 17 Ball Diagram P/PG-LBGA-160-1 bottom view 17 Pin Diagram P-TQFP-144 19 Pin Definitions and Functions 20 Pin Strapping 64 Functional Description 65 Hardware 65 Software 66 Functional Overview 66 Block Diagram 67 Functional Blocks 67 Asynchronous Micro Controller Interface Intel or Motorola mode 67 Mixed Byte/Word Access 68 Serial Micro Controller Interfaces 69 SCI Interface 69 SPI Interface 73 Interrupt Interface 74 Boundary Scan Interface 76 Master Clocking Unit 78 PLL Reset and Configuring 79 Line Coding and Framer Interface Modes 80 Bipolar Violation Detection 81 Receive Path 83 Receive Line Interface 84 Receive Line Coding 84 Receive Line Interface 84 “Generic” Receiver Interface 85 Receive Line Monitoring Mode RLM 86 Monitoring Application using RLM 86 Redundancy Application using RLM 87 General Redundancy Applications 89 Loss-of-Signal Detection 91 Receive Equalization Network 92 Receive Line Attenuation Indication 92 Receive Clock and Data Recovery 92 Receive Jitter Attenuator 92 Receive Jitter Attenuation Performance 95 Jitter Tolerance E1 96 Output Jitter 98 Output Wander 98 Dual Receive Elastic Buffer 99 Additional Receiver Functions 100 Error Monitoring and Alarm Handling 100 Automatic Modes 101 Error Counter 101 One-Second Timer 101 Data Sheet QuadLIUTM PEF 22504 Table of Contents Transmit Path 102 Transmit Line Interface 102 Transmit Clock TCLK 103 Automatic Transmit Clock Switching 103 Transmit Jitter Attenuator 104 Dual Transmit Elastic Buffer 105 Programmable Pulse Shaper and Line Build-Out 105 QuadFALCTM V2.1 Compatible Programming with XPM 2:0 Registers 106 Programming with TXP 16:1 Registers 107 Transmit Line Monitor 108 Framer Interface 109 Test Functions 110 Pseudo-Random Binary Sequence Generation and Monitor 110 In-Band Loop Generation, Detection and Loop Switching 111 Remote Loop 112 Local Loop 113 Payload Loop-Back 113 Alarm Simulation 114 Multi Function Ports 114 Register Description 116 Detailed Control Register Description 116 Control Registers 120 Detailed Status Register Description 191 Transmit Clock TCLK Frequency Selection See Chapter Note that frequencies are not in ascent ordering. 000B MHz. 001B MHz. 010B MHz. 011B MHz. 100B MHz. 101B reserved. 110B reserved. 111B reserved. Data Sheet Field SCFX ATCS QuadLIUTM PEF 22504 Register DescriptionClock Mode Register 6 Bits Type Description Select Corner Frequency of DCO-X Only applicable if CMR2.EXFAX = See Chapter and 0B corner frequency of DCO-X is 2 Hz. 1B corner frequency of DCO-X is Hz. Automatic Transmit Clock Switching See Chapter If TCLK is lost, automatically switching to FCLKX can be performed. Note Kind of used transmit clock source is shown in status register XCLKS. 0B automatic clock switching is disabled. 1B automatic clock switching is enabled. Data Sheet Clock Mode Register 1 QuadLIUTM PEF 22504 Register DescriptionClock Mode Register 1 CMR1 Clock Mode Register 1 Offset xx44H Reset Value 00H ';66 Field DCS DXJA DXSS Bits Type Description Disable Clock-Switching In Slave mode LIM0.MAS = the DCO-R is synchronized on the recovered route clock. In case of loss-of-signal LOS the DCO-R switches automatically to the clock sourced by port SYNC. 0B automatic switching from RCLK to SYNC is enabled 1B automatic switching from RCLK to SYNC is disabled Disable Internal Transmit Jitter Attenuation Setting this bit disables the transmit jitter attenuation. Reading the data out of the transmit elastic buffer and transmitting on XL1/2 XDOP/N/XOID is done with the clock provided on pin TCLK. In transmit elastic buffer bypass mode the transmit clock is taken from FCLKX, independent of this bit. DCO-X Synchronization Clock Source

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QuadLIUTM

Quad E1/T1/J1 Line Interface Component for Long- and Short-Haul Applications PEF 22504 E, PEF 22504 HT, Version

Communications

Edition 2006-01-25

Published by Infineon Technologies AG, 81726 München, Germany Infineon Technologies AG All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

QuadLIUTM PEF 22504

PEF 22504 E, Quad E1/T1/J1 Line Interface Component for Long- and Short-Haul Applications

Previous Version Preliminary Data Sheet 2005-11-07

Chapter 5

The QuadLIUTM is now available in PG-TQFP-144-17 package also

Trademarks
are registered trademarks of Infineon Technologies AG. 10BaseS , EasyPort , VDSLite are trademarks of Infineon Technologies AG. is a registered trademark of Microsoft Corporation, of Linus Torvalds, of Visio Corporation, and of Adobe Systems

Incorporated.

Data Sheet

QuadLIUTM PEF 22504

Table of Contents

Preface 11

Introduction 12 Features 13 Logic Symbol 15 Typical Applications 16

Pin Descriptions 17 Ball Diagram P/PG-LBGA-160-1 top view 17 Ball Diagram P/PG-LBGA-160-1 bottom view 17 Pin Diagram P-TQFP-144 19 Pin Definitions and Functions 20 Pin Strapping 64

Functional Description 65 Hardware 65 Software 66 Functional Overview 66 Block Diagram 67 Functional Blocks 67

Asynchronous Micro Controller Interface Intel or Motorola mode 67 Mixed Byte/Word Access 68

Serial Micro Controller Interfaces 69 SCI Interface 69 SPI Interface 73

Interrupt Interface 74 Boundary Scan Interface 76 Master Clocking Unit 78

PLL Reset and Configuring 79 Line Coding and Framer Interface Modes 80

Bipolar Violation Detection 81 Receive Path 83

Receive Line Interface 84 Receive Line Coding 84 Receive Line Interface 84
“Generic” Receiver Interface 85 Receive Line Monitoring Mode RLM 86 Monitoring Application using RLM 86 Redundancy Application using RLM 87 General Redundancy Applications 89 Loss-of-Signal Detection 91 Receive Equalization Network 92 Receive Line Attenuation Indication 92 Receive Clock and Data Recovery 92 Receive Jitter Attenuator 92 Receive Jitter Attenuation Performance 95 Jitter Tolerance E1 96 Output Jitter 98 Output Wander 98 Dual Receive Elastic Buffer 99 Additional Receiver Functions 100 Error Monitoring and Alarm Handling 100 Automatic Modes 101 Error Counter 101 One-Second Timer 101

Data Sheet

QuadLIUTM PEF 22504

Table of Contents

Transmit Path 102 Transmit Line Interface 102 Transmit Clock TCLK 103 Automatic Transmit Clock Switching 103 Transmit Jitter Attenuator 104 Dual Transmit Elastic Buffer 105 Programmable Pulse Shaper and Line Build-Out 105 QuadFALCTM V2.1 Compatible Programming with XPM 2:0 Registers 106 Programming with TXP 16:1 Registers 107 Transmit Line Monitor 108

Framer Interface 109 Test Functions 110

Pseudo-Random Binary Sequence Generation and Monitor 110 In-Band Loop Generation, Detection and Loop Switching 111 Remote Loop 112 Local Loop 113 Payload Loop-Back 113 Alarm Simulation 114 Multi Function Ports 114

Register Description 116 Detailed Control Register Description 116

Control Registers 120 Detailed Status Register Description 191
Transmit Clock TCLK Frequency Selection See Chapter Note that frequencies are not in ascent ordering. 000B MHz. 001B MHz. 010B MHz. 011B MHz. 100B MHz. 101B reserved. 110B reserved. 111B reserved.

Data Sheet

Field SCFX

ATCS

QuadLIUTM PEF 22504

Register DescriptionClock Mode Register 6

Bits

Type Description

Select Corner Frequency of DCO-X

Only applicable if CMR2.EXFAX = See Chapter and
0B corner frequency of DCO-X is 2 Hz. 1B corner frequency of DCO-X is Hz.

Automatic Transmit Clock Switching

See Chapter If TCLK is lost, automatically switching to FCLKX can
be performed.

Note Kind of used transmit clock source is shown in status register XCLKS.
0B automatic clock switching is disabled. 1B automatic clock switching is enabled.

Data Sheet

Clock Mode Register 1

QuadLIUTM PEF 22504

Register DescriptionClock Mode Register 1

CMR1 Clock Mode Register 1

Offset xx44H

Reset Value 00H
';66

Field DCS

DXJA

DXSS

Bits

Type Description

Disable Clock-Switching

In Slave mode LIM0.MAS = the DCO-R is synchronized on the
recovered route clock. In case of loss-of-signal LOS the DCO-R switches
automatically to the clock sourced by port SYNC.
0B automatic switching from RCLK to SYNC is enabled 1B automatic switching from RCLK to SYNC is disabled

Disable Internal Transmit Jitter Attenuation

Setting this bit disables the transmit jitter attenuation. Reading the data
out of the transmit elastic buffer and transmitting on XL1/2

XDOP/N/XOID is done with the clock provided on pin TCLK. In transmit
elastic buffer bypass mode the transmit clock is taken from FCLKX,
independent of this bit.

DCO-X Synchronization Clock Source

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived PEF22504HTV2.1 Datasheet file may be downloaded here without warranties.

Datasheet ID: PEF22504HTV2.1 638460