PEF 22552 E V1.1
PEF 22552 E V1.1 Datasheet
Two-channel E1/T1/J1 Framer and Line Interface Component PEF 22552
| Part | Datasheet |
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PEF 22552 E V1.1 |
PEF 22552 E V1.1 (pdf) |
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| D u a l FA L C TM Two-channel E1/T1/J1 Framer and Line Interface Component PEF 22552 The DualFALCTM is an addition to Infineon's market leading family of advanced E1/T1/J1 Framer And Line Interface Unit LIU components. As a two port E1/T1/J1 framer and line interface unit LIU , DualFALC is optimized for a range of network equipment including Radio network Controllers, Node B line cards, PBX or SDH/SONET ADMs. The DualFALC features a unique clock generation unit that accepts any reference clock between and 20MHz as well as integrated analog switches for impedance matching or protection switching. Using industry leading DualFALC Evaluation support tools, system developers can shorten design cycles while creating a wide range of highly flexible, low BOM E1/T1/J1 line cards. • Wireless base stations • Router • Multi-service access platforms, • Digital loop carriers • Remote access servers/concentrators • SONET/SDH Add/Drop multiplexers Analog Line Interfaces • Two independent E1/T1/J1 long haul/short haul line interface units • Software programmable T1/E1/J1 • Integrated analog switches for impedance matching E1-75/120, T1-100 , J1-110 and protection switching • Crystal-less wander and jitter attenuation/compensation according to TR 62411 and ETS-TBR 12/13 • Clock generation unit accepts any frequency reference clock from MHz to 20 MHz • Programmable transmit pulse shape for flexible pulse generation • Receiver sensitivity exceeds -36 and -43 • Clock signal generation & extraction according to ITU-T G.703 Sec. 13 • Integrated transmit line impedance matching Frame Aligners • ITU-T G.704 frame alignment/synthesis for Mbit/s w. i n f i n e o n c o m / f a l c • Programmable frame formats E1 Double- & CRC Multi-frame T1 F4, F12 D4 , Ext. Super Frame ESF , F72 SLC96 • Detects and generates LOS, AIS and RAI alarms • CRC-4 performance monitoring • PRBS generation and monitoring • Detects & generates LOS, AIS & RAI alarms • System bus data rate scalable from Mbit/s up to 16 Mb/s • Synchronization Supply Message SSM generation and extraction HDLC Controllers • 6 HDLC controllers three per channel including 128-byte deep FIFO buffers each • CAS controller with micro-processor or system interface serial access • Supports signaling system #7 • ANSI T1.403 Bit-Oriented Messages BOM , generates periodical performance reports General Features • Software compatible to Infineon’s QuadFALC and OctalFALC • or type 8/16-bit microprocessor interface • Serial SPI bus and serial SCI bus slave interfaces • Low power operation 150mW / channel typical • Dual voltage V/3.3 V or single voltage 3.3V power supply • PG-LBGA-160, 15x15mm with 1.0mm ball pitch • -40degC to +85degC operation • Rohs compliant package Communications Never stop thinking. DualFALC PEF 22552 Block Diagram Transmission Line Local Loop Remote Loop Payload Loop Switching Network Long/Short Haul Receive Line Interface Transmit Line Interface Clock Receive Framer Alarm Detection PRBS Monitor Line Decoder Ordering No. B000-H0000-X-X-7600 Printed in Germany PS KS |
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