PEB 20256 E V2.2

PEB 20256 E V2.2 Datasheet

MUNICH256 Multichannel Network Interface Controller for HDLC/PPP PEB 20256 E Version

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PEB 20256 E V2.2	PEB 20256 E V2.2 (pdf)

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Data Sheet, DS2, April 2001 MUNICH256 Multichannel Network Interface Controller for HDLC/PPP PEB 20256 E Version Datacom Never stop thinking. Edition Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany Infineon Technologies AG All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide see address list . Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Data Sheet, DS2, April 2001 MUNICH256 Multichannel Network Interface Controller for HDLC/PPP PEB 20256 E Version Datacom Never stop thinking. PEB 20256 E PEF 20256 E Previous Version: Preliminary Data Sheet Major changes to document since last version Page 25 26 54 154 159 190 203 206 207 210 211 215 218 Description Pin Diagram added 16-Port mode Pin Diagram added 28-Port mode Remote payload loop block diagram redrawn Swap the bit positions of TBRTC and TBFTC In the CSPEC_BUFFER register as their bit postitions were not correct in the preliminary data sheet. Swap the postions of TBRTC with TBFTC in Table 8-7, as their column positions were not correct in the preliminary data sheet Fixed typo in CSPEC_IMASK register, replaced ROFD with RFOD Fixed typo in IQMASK, replaced ROFD with RFOD Update voltage min/max information for Table 9-1 Absolute Maximum Ratings Update timing Information for Table 9-4 DC Characteristics PCI Interface Pins Update timing Information for Table 9-5 PCI Clock Characteristics Update timing Information for Table 9-6 PCI Interface Signal Characteristics Update timing Information for Table 9-8 Intel Bus Interface Timing Intel Bus Interface Timing Diagram modified. The setup and hold times for “LD to LRDY” was not a valid timing parameter. Instead, the setup and hold parameters for “LD to LRD” were specified. Update timing Information for Table 9-9 Intel Bus Interface Timing Master Mode Timing parameter setup time 67a was changed from “LD to LDRY” to ”LD to LRD”, because it was not a valid timing parameter. Timing parameter hold time 67b was changed from “LD to LDRY” to ”LD to LRD”, because it was not a valid timing parameter. Update timing Information for Table 9-10 Motorola Bus Interface Timing Update timing Information for Table 9-11 Motorola Bus Interface Timing Master Mode Data Sheet PEB 20256 E PEF 20256 E For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide see our webpage at Data Sheet Selectable port configuration 51 External Timing Mode 52 Local Port Loop 53 Remote Payload Loop 54 Remote Channel Loopback 55 Test Breakout 56 Time slot Handler 57 Channelized Modes 57 Unchannelized Mode 58 Data Management Unit 59 Descriptor Concept 59 Receive Descriptor 60 Data Management Unit Receive 64 Transmit Descriptor 66 Data Management Unit Transmit 69 Byte Swapping 71 Transmission Bit/Byte Ordering 72 Buffer Management 72 Internal Receive Buffer 72 Data Sheet PEB 20256 E PEF 20256 E Table of Contents Internal Transmit Buffer 74 Protocol Description 76 HDLC Mode 76 Bit Synchronous PPP with HDLC Framing Structure 77 Octet Synchronous PPP 77 Transparent Mode 78 Mailbox 78 Interrupt Controller 80 Layer Two interrupts 80 General Interrupt Vector Structure 82 System Interrupts 84 Port Interrupts 85 Channel Interrupts 87 Command Interrupts 92 Mailbox Interrupts to the Local Bus 94 Interface Description 96 PCI Interface 96 PCI Read Transaction 96 PCI Write Transaction 97 SPI Interface ROM Load Unit 98 Accesses to a SPI EEPROM 99 SPI Read Sequence 99 SPI Write Sequence 100 Local Microprocessor Interface 101 Intel Mode 102 Slave Mode 102 Master Mode 102 Motorola Mode 105 Slave Mode 105 Master Mode 105 Serial Line Interface 107 Interface Timing in 16-port mode 108 Interface Timing in 28-port mode 111 JTAG Interface 112 Channel Programming / Reprogramming Concept 115 Channel Commands 116 Transmit Channel Commands 116 Receive Channel Commands 118 Reset and Initialization procedure 121 Chip Initialization 121 Mode Initialization 122 Data Sheet PEB 20256 E PEF 20256 E Table of Contents Register Description 123 Register Overview 123 PCI Configuration Register Set Direct Access 123 PCI Slave Register Set Direct Access 125 PCI and Local Bus Register Set Direct Access 127 Detailed Register Description 129 PCI Configuration Register 129 PCI Slave Register 144 Serial Interface Timing 161 Clock Input Timing 161 Transmit Cycle Timing 161 Transmit Synchronization Timing 161 Receive Cycle Timing 161 Receive Synchronization Timing 161 Interface Timing in 16-port mode 161 Interface Timing in 28-port mode 161 Mailbox Interrupts to the Local Bus 161 Selectable port configuration 161 External Timing Mode 161 Local Port Loop 161 Remote Payload Loop 161 Remote Channel Loopback 161 Test Breakout 161 Serial Interface 16-port mode 161 Serial Interface 28-port mode 161 Pin Diagram 16-Port Mode MUNICH256 161 Pin Diagram 28-Port Mode MUNICH256 161 General System Integration MUNICH256 161 General Features 161 PCI and Local Bus Slave Register Set 194 Electrical Characteristics 203 Important Electrical Requirements 203 Absolute Maximum Ratings 203 DC Characteristics 203 AC Characteristics 205 PCI Bus Interface Timing 206 SPI Interface Timing 208 Local Microprocessor Interface Timing 209 Intel Bus Interface Timing Slave Mode 209 Intel Bus Interface Timing Master Mode 211 Motorola Bus Interface Timing Slave Mode 214 Motorola Bus Interface Timing Master Mode 216 Data Sheet PEB 20256 E PEF 20256 E Serial Interface Timing 220 Clock Input Timing 220 Transmit Cycle Timing 221 Transmit Synchronization Timing 222 Receive Cycle Timing 223 Receive Synchronization Timing 224 JTAG Interface Timing 225 Reset Timing 226 Package Outline 227 List of Abbreviations 229 Data Sheet PEB 20256 E PEF 20256 E List of Figures Figure 1-1 Figure 1-2 Figure 1-3 Figure 2-1 Figure 2-2 Figure 3-1 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 4-7 Figure 4-8 Figure 4-9 Figure 4-10 Figure 4-11 Figure 4-12 Figure 4-13 Figure 4-14 Figure 4-15 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Figure 5-6 Figure 5-7 Figure 5-8 Figure 5-9 Figure 5-10 Figure 5-11 Figure 5-12 Figure 5-13 Figure 5-14 Figure 5-15 Figure 8-1 Figure 8-2 Figure 8-3 Figure 8-4 Figure 8-5 Figure 8-6 MUNICH256 16-port Mode Logic Symbol 22 MUNICH256 28-port Mode Logic Symbol 23 System Integration of the MUNICH256 24 MUNICH256 Pin Configuration 16-Port Mode 25 MUNICH256 Pin Configuration 28-Port Mode 26 MUNICH256 Block Diagram 47 Port Configuration 52 Local Port Loop 53 Remote Payload Loop 54 Remote Channel Loop 55 Test Breakout 56 Time slot Assignment in Channelized Modes 58 Descriptor Structure 60 Receive Buffer Thresholds 74 Transmit Buffer Thresholds 75 HDLC Frame Format 76 Bit Synchronous PPP with HDLC Framing Structure. 77 Mailbox Structure 79 Layer Two Interrupts Channel, command, port and system interrupts 81 Interrupt Queue Structure in System Memory 82 Mailbox Interrupt Notification 94 PCI Read Transaction 97 PCI Write Transaction 98 SPI Read Sequence 100 SPI Write Sequence. 100 Intel Bus Mode 103 Intel Bus Arbitration 103 Motorola Bus Mode 106 Motorola Bus Arbitration 106 Supported Frame Structures 108 T1 Mode Frame Timing 109 E1, MHz and MHz Interface Timing in 16-port mode 110 Unchannelized Mode Interface Timing 111 T1-mode Interface Timing in 28-port Mode 111 E1-mode Interface Timing in 28-port Mode 112 Block Diagram of Test Access Port and Boundary Scan Unit 113 Clock Input Timing 161 Transmit Cycle Timing 161 Transmit Synchronization Timing. 161 Receive Cycle Timing 161 Receive Synchronization Timing 161 Supported Frame Structures 161 Data Sheet PEB 20256 E PEF 20256 E List of Figures Figure 8-7 Figure 8-8 Figure 8-9 Figure 8-10 Figure 8-11 Figure 8-12 Figure 8-13 Figure 8-14 Figure 8-15 Figure 8-16 Figure 8-17 Figure 8-18 Figure 8-19 Figure 8-20 Figure 8-21 Figure 8-22 Figure 8-23 Figure 9-1 Figure 9-2 Figure 9-3 Figure 9-4 Figure 9-5 Figure 9-6 Figure 9-7 Figure 9-8 Figure 9-9 Figure 9-10 Figure 9-11 Figure 9-12 Figure 9-13 Figure 9-14 Figure 9-15 Figure 9-16 Figure 9-17 Figure 9-18 Figure 9-19 Figure 9-20 Figure 9-21 Figure 9-22 Figure 9-23 Figure 9-24 Figure 9-25 Note Byte swapping only effects the organization of packet data in system memory. All internal registers, as well as the descriptors, address pointers or interrupt vectors are handled with little endian byte ordering. Data Sheet Table 4-4 BNO 3 PEB 20256 E PEF 20256 E Functional Description Example for little/big Endian with BNO = 3 Little Endian Big Endian Byte 2 Byte 1 Byte 0 Byte 0 Byte 1 Byte 2 Table 4-5 Example for little big Endian with BNO = 7 BNO 7 Byte3 - Little Endian Byte 2 Byte 1 Byte 6 Byte 5 Byte 0 Byte 4 Byte 0 Byte 4 Big Endian Byte 1 Byte 2 Byte 5 Byte 6 Byte3 - Transmission Bit/Byte Ordering Data is transmitted beginning with byte zero in increasing order. Vice versa data received is stored starting with byte zero. The position of byte zero depends on the selected endian mode. Each byte itself consists of eight bits starting with bit zero LSB up to bit seven MSB . Data on the serial line is transmitted starting with the LSB. The first bit received is stored in bit zero. Buffer Management Internal Receive Buffer The internal receive buffer provides buffering of frame data and status between the protocol handler and the receive data management units. Internal buffers are essential to avoid data loss due to the PCI bus latency, especially in the presence of multiple devices on the same PCI bus, and to enable a minimized bus utilization through burst accesses. The incoming data from the protocol handler is stored in a receive central buffer shared by all the 256 channels. The buffer is written by the protocol handler every time a complete DWORD is ready or the last byte of a frame has been received. Each channel has an individual programmable threshold code, which determines after how many DWORDs a data transfer into the shared memory is generated. The threshold therefore defines the maximum burst length for a particular channel in receive direction. A data transfer is also requested as soon as a frame end has been reached. Programming the burst length to be greater than 1 DWORD avoids too frequent accesses to the PCI bus, thereby optimizing use of this resource. For real time channels with lowest possible latency example constant bit rate a value of one DWORD can be selected for the burst length. Data Sheet PEB 20256 E PEF 20256 E Functional Description The total size of the internal receive buffer is 12 kByte. If all the 256 channels are active, the average burst threshold should be programmed with 8 DWORDs, so that 4 DWORDs are available on the average to compensate for PCI latency and avoid data loss. However if less than 256 channels are active or if only 64 KBit/s channels are used, the burst threshold may be programmed to a higher value. In other words, the sum of all channel thresholds shall not exceed the maximum receive buffer locations. In order to prevent an overload condition from one particular channel e.g. receiving only small or invalid frames , the receive buffer provides the capability to delete frames which are smaller or equal than a programmable threshold. All frames that have been dropped will be counted and an interrupt vector will be generated as soon as a programmable threshold has been reached. The actual value of the counter can be read in the small frame dropped counter register. Data Sheet protocol machine receive buffer receive burst threshold PEB 20256 E PEF 20256 E Functional Description protocol machine receive buffer 2nd burst delete receive burst threshold frame minimum frame length data management unit 1st burst receive burst threshold minimum frame length frame data management unit Example A Normal operation Example B Drop of small frames Figure 4-8 Receive Buffer Thresholds For performance monitoring the receive buffer provides the capability to monitor the receive buffer utilization and to generate interrupts when certain fill thresholds have been reached. Internal Transmit Buffer The internal transmit buffer with a total size of 32 kByte stores protocol data before it is processed by the protocol machine. The transmit buffer is essential to ensure that enough data is available during transmission, since PCI latency and usage of multiple Data Sheet PEB 20256 E PEF 20256 E Functional Description channels limit access to system memory for a particular channel. A programmable transmit buffer size and two programmable threshold are configurable by the host CPU for each channel. Note The sum of both thresholds must be smaller than the transmit buffer size of a particular channel. protocol machine transmit buffer

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Data Sheet, DS2, April 2001

MUNICH256 Multichannel Network Interface Controller for HDLC/PPP PEB 20256 E Version

Datacom

Never stop thinking.

Edition

Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany

Infineon Technologies AG

All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide see address list .

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Data Sheet, DS2, April 2001

MUNICH256 Multichannel Network Interface Controller for HDLC/PPP PEB 20256 E Version

Datacom

Never stop thinking.

PEB 20256 E PEF 20256 E

Previous Version:

Preliminary Data Sheet

Major changes to document since last version

Page 25 26 54 154
159 190 203
206 207
210 211
215 218

Description Pin Diagram added 16-Port mode

Pin Diagram added 28-Port mode

Remote payload loop block diagram redrawn Swap the bit positions of TBRTC and TBFTC In the CSPEC_BUFFER register as their bit postitions were not correct in the preliminary data sheet.

Swap the postions of TBRTC with TBFTC in Table 8-7, as their column positions were not correct in the preliminary data sheet

Fixed typo in CSPEC_IMASK register, replaced ROFD with RFOD

Fixed typo in IQMASK, replaced ROFD with RFOD Update voltage min/max information for Table 9-1 Absolute Maximum Ratings Update timing Information for Table 9-4 DC Characteristics PCI Interface Pins

Update timing Information for Table 9-5 PCI Clock Characteristics Update timing Information for Table 9-6 PCI Interface Signal Characteristics

Update timing Information for Table 9-8 Intel Bus Interface Timing Intel Bus Interface Timing Diagram modified. The setup and hold times for “LD to LRDY” was not a valid timing parameter. Instead, the setup and hold parameters for “LD to LRD” were specified.

Update timing Information for Table 9-9 Intel Bus Interface Timing Master Mode Timing parameter setup time 67a was changed from “LD to LDRY” to ”LD to LRD”, because it was not a valid timing parameter. Timing parameter hold time 67b was changed from “LD to LDRY” to ”LD to LRD”, because it was not a valid timing parameter.

Update timing Information for Table 9-10 Motorola Bus Interface Timing Update timing Information for Table 9-11 Motorola Bus Interface Timing Master Mode

Data Sheet

PEB 20256 E PEF 20256 E

For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide see our webpage at

Data Sheet
Selectable port configuration 51 External Timing Mode 52 Local Port Loop 53 Remote Payload Loop 54 Remote Channel Loopback 55 Test Breakout 56 Time slot Handler 57 Channelized Modes 57 Unchannelized Mode 58 Data Management Unit 59 Descriptor Concept 59 Receive Descriptor 60 Data Management Unit Receive 64 Transmit Descriptor 66 Data Management Unit Transmit 69 Byte Swapping 71 Transmission Bit/Byte Ordering 72 Buffer Management 72 Internal Receive Buffer 72

Data Sheet

PEB 20256 E PEF 20256 E

Table of Contents

Internal Transmit Buffer 74 Protocol Description 76

HDLC Mode 76 Bit Synchronous PPP with HDLC Framing Structure 77 Octet Synchronous PPP 77 Transparent Mode 78 Mailbox 78 Interrupt Controller 80 Layer Two interrupts 80

General Interrupt Vector Structure 82 System Interrupts 84 Port Interrupts 85 Channel Interrupts 87 Command Interrupts 92 Mailbox Interrupts to the Local Bus 94

Interface Description 96 PCI Interface 96

PCI Read Transaction 96 PCI Write Transaction 97 SPI Interface ROM Load Unit 98 Accesses to a SPI EEPROM 99 SPI Read Sequence 99 SPI Write Sequence 100 Local Microprocessor Interface 101 Intel Mode 102

Slave Mode 102 Master Mode 102 Motorola Mode 105 Slave Mode 105 Master Mode 105 Serial Line Interface 107 Interface Timing in 16-port mode 108 Interface Timing in 28-port mode 111 JTAG Interface 112

Channel Programming / Reprogramming Concept 115

Channel Commands 116

Transmit Channel Commands 116

Receive Channel Commands 118

Reset and Initialization procedure 121

Chip Initialization 121

Mode Initialization 122

Data Sheet

PEB 20256 E PEF 20256 E

Table of Contents

Register Description 123 Register Overview 123

PCI Configuration Register Set Direct Access 123 PCI Slave Register Set Direct Access 125 PCI and Local Bus Register Set Direct Access 127 Detailed Register Description 129 PCI Configuration Register 129 PCI Slave Register 144 Serial Interface Timing 161

Clock Input Timing 161 Transmit Cycle Timing 161 Transmit Synchronization Timing 161 Receive Cycle Timing 161 Receive Synchronization Timing 161 Interface Timing in 16-port mode 161 Interface Timing in 28-port mode 161 Mailbox Interrupts to the Local Bus 161 Selectable port configuration 161 External Timing Mode 161 Local Port Loop 161 Remote Payload Loop 161 Remote Channel Loopback 161 Test Breakout 161 Serial Interface 16-port mode 161 Serial Interface 28-port mode 161 Pin Diagram 16-Port Mode MUNICH256 161 Pin Diagram 28-Port Mode MUNICH256 161 General System Integration MUNICH256 161 General Features 161 PCI and Local Bus Slave Register Set 194

Electrical Characteristics 203 Important Electrical Requirements 203 Absolute Maximum Ratings 203 DC Characteristics 203 AC Characteristics 205

PCI Bus Interface Timing 206 SPI Interface Timing 208 Local Microprocessor Interface Timing 209

Intel Bus Interface Timing Slave Mode 209 Intel Bus Interface Timing Master Mode 211 Motorola Bus Interface Timing Slave Mode 214 Motorola Bus Interface Timing Master Mode 216

Data Sheet

PEB 20256 E PEF 20256 E

Serial Interface Timing 220 Clock Input Timing 220 Transmit Cycle Timing 221 Transmit Synchronization Timing 222 Receive Cycle Timing 223 Receive Synchronization Timing 224

JTAG Interface Timing 225 Reset Timing 226

Package Outline 227

List of Abbreviations 229

Data Sheet

PEB 20256 E PEF 20256 E

List of Figures

Figure 1-1 Figure 1-2 Figure 1-3 Figure 2-1 Figure 2-2 Figure 3-1 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 4-7 Figure 4-8 Figure 4-9 Figure 4-10 Figure 4-11 Figure 4-12 Figure 4-13 Figure 4-14 Figure 4-15 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Figure 5-6 Figure 5-7 Figure 5-8 Figure 5-9 Figure 5-10 Figure 5-11 Figure 5-12 Figure 5-13 Figure 5-14 Figure 5-15 Figure 8-1 Figure 8-2 Figure 8-3 Figure 8-4 Figure 8-5 Figure 8-6

MUNICH256 16-port Mode Logic Symbol 22 MUNICH256 28-port Mode Logic Symbol 23 System Integration of the MUNICH256 24 MUNICH256 Pin Configuration 16-Port Mode 25 MUNICH256 Pin Configuration 28-Port Mode 26 MUNICH256 Block Diagram 47 Port Configuration 52 Local Port Loop 53 Remote Payload Loop 54 Remote Channel Loop 55 Test Breakout 56 Time slot Assignment in Channelized Modes 58 Descriptor Structure 60 Receive Buffer Thresholds 74 Transmit Buffer Thresholds 75 HDLC Frame Format 76 Bit Synchronous PPP with HDLC Framing Structure. 77 Mailbox Structure 79 Layer Two Interrupts Channel, command, port and system interrupts 81 Interrupt Queue Structure in System Memory 82 Mailbox Interrupt Notification 94 PCI Read Transaction 97 PCI Write Transaction 98 SPI Read Sequence 100 SPI Write Sequence. 100 Intel Bus Mode 103 Intel Bus Arbitration 103 Motorola Bus Mode 106 Motorola Bus Arbitration 106 Supported Frame Structures 108 T1 Mode Frame Timing 109 E1, MHz and MHz Interface Timing in 16-port mode 110 Unchannelized Mode Interface Timing 111 T1-mode Interface Timing in 28-port Mode 111 E1-mode Interface Timing in 28-port Mode 112 Block Diagram of Test Access Port and Boundary Scan Unit 113 Clock Input Timing 161 Transmit Cycle Timing 161 Transmit Synchronization Timing. 161 Receive Cycle Timing 161 Receive Synchronization Timing 161 Supported Frame Structures 161

Data Sheet

PEB 20256 E PEF 20256 E

List of Figures

Figure 8-7 Figure 8-8 Figure 8-9 Figure 8-10 Figure 8-11 Figure 8-12 Figure 8-13 Figure 8-14 Figure 8-15 Figure 8-16 Figure 8-17 Figure 8-18 Figure 8-19 Figure 8-20 Figure 8-21 Figure 8-22 Figure 8-23 Figure 9-1 Figure 9-2 Figure 9-3 Figure 9-4 Figure 9-5 Figure 9-6 Figure 9-7 Figure 9-8 Figure 9-9 Figure 9-10 Figure 9-11 Figure 9-12 Figure 9-13 Figure 9-14 Figure 9-15 Figure 9-16 Figure 9-17 Figure 9-18 Figure 9-19 Figure 9-20 Figure 9-21 Figure 9-22 Figure 9-23 Figure 9-24 Figure 9-25
Note Byte swapping only effects the organization of packet data in system memory. All internal registers, as well as the descriptors, address pointers or interrupt vectors are handled with little endian byte ordering.

Data Sheet

Table 4-4 BNO 3

PEB 20256 E PEF 20256 E

Functional Description

Example for little/big Endian with BNO = 3

Little Endian

Big Endian

Byte 2 Byte 1 Byte 0 Byte 0 Byte 1 Byte 2

Table 4-5 Example for little big Endian with BNO = 7

BNO 7

Byte3 -

Little Endian Byte 2 Byte 1 Byte 6 Byte 5

Byte 0 Byte 4

Byte 0 Byte 4

Big Endian Byte 1 Byte 2 Byte 5 Byte 6

Byte3 -
Transmission Bit/Byte Ordering

Data is transmitted beginning with byte zero in increasing order. Vice versa data received is stored starting with byte zero. The position of byte zero depends on the selected endian mode.

Each byte itself consists of eight bits starting with bit zero LSB up to bit seven MSB . Data on the serial line is transmitted starting with the LSB. The first bit received is stored in bit zero.

Buffer Management

Internal Receive Buffer

The internal receive buffer provides buffering of frame data and status between the protocol handler and the receive data management units. Internal buffers are essential to avoid data loss due to the PCI bus latency, especially in the presence of multiple devices on the same PCI bus, and to enable a minimized bus utilization through burst accesses.

The incoming data from the protocol handler is stored in a receive central buffer shared by all the 256 channels. The buffer is written by the protocol handler every time a complete DWORD is ready or the last byte of a frame has been received. Each channel has an individual programmable threshold code, which determines after how many DWORDs a data transfer into the shared memory is generated. The threshold therefore defines the maximum burst length for a particular channel in receive direction. A data transfer is also requested as soon as a frame end has been reached. Programming the burst length to be greater than 1 DWORD avoids too frequent accesses to the PCI bus, thereby optimizing use of this resource.

For real time channels with lowest possible latency example constant bit rate a value of one DWORD can be selected for the burst length.

Data Sheet

PEB 20256 E PEF 20256 E

Functional Description

The total size of the internal receive buffer is 12 kByte. If all the 256 channels are active, the average burst threshold should be programmed with 8 DWORDs, so that 4 DWORDs are available on the average to compensate for PCI latency and avoid data loss. However if less than 256 channels are active or if only 64 KBit/s channels are used, the burst threshold may be programmed to a higher value. In other words, the sum of all channel thresholds shall not exceed the maximum receive buffer locations.

In order to prevent an overload condition from one particular channel e.g. receiving only small or invalid frames , the receive buffer provides the capability to delete frames which are smaller or equal than a programmable threshold. All frames that have been dropped will be counted and an interrupt vector will be generated as soon as a programmable threshold has been reached. The actual value of the counter can be read in the small frame dropped counter register.

Data Sheet
protocol machine receive buffer
receive burst threshold

PEB 20256 E PEF 20256 E

Functional Description
protocol machine receive buffer
2nd burst
delete
receive burst threshold
frame
minimum frame length
data management unit
1st burst
receive burst threshold minimum frame length
frame data management unit

Example A Normal operation

Example B Drop of small frames

Figure 4-8 Receive Buffer Thresholds

For performance monitoring the receive buffer provides the capability to monitor the receive buffer utilization and to generate interrupts when certain fill thresholds have been reached.

Internal Transmit Buffer

The internal transmit buffer with a total size of 32 kByte stores protocol data before it is processed by the protocol machine. The transmit buffer is essential to ensure that enough data is available during transmission, since PCI latency and usage of multiple

Data Sheet

PEB 20256 E PEF 20256 E

Functional Description
channels limit access to system memory for a particular channel. A programmable transmit buffer size and two programmable threshold are configurable by the host CPU for each channel. Note The sum of both thresholds must be smaller than the transmit buffer size of a
particular channel.
protocol machine
transmit buffer

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived PEB20256EV2.2 Datasheet file may be downloaded here without warranties.

Datasheet ID: PEB20256EV2.2 638408